参数资料
型号: LTC3872IDDB#TRPBF
厂商: Linear Technology
文件页数: 15/22页
文件大小: 0K
描述: IC REG CTRLR BST PWM CM 8-DFN
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 650kHz
电源电压: 2.75 V ~ 9.8 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 8-WFDFN 裸露焊盘
包装: 带卷 (TR)
LTC3872
APPLICATIONS INFORMATION
V IN(MIN) 3.3V
R DS(ON) ≤ V S ENS E(MAX) ?
? 1+ χ ? ? I ? ρ T
≈ 30m ?
= 0.175V ?
? 1+ 0.4 ? ? 2A ? 1.5
And so the inductor value is:
L= ? D MAX = ? 0.39 = 1.8μH
?I L ? f 1.3A ? 550kHz
The component chosen is a 2.2μH inductor made by
Sumida (part number CEP125-H 1ROMH).
3. Assuming a MOSFET junction temperature of 125°C,
the room temperature MOSFET R DS(ON) should be less
than:
1–D MAX
? 2 ? O(MAX)
1– 0.39
? 2 ?
The MOSFET used was the Si3460, which has a maximum
R DS(ON) of 27m Ω at 4.5V V GS , a BV DSS of greater than
30V, and a gate charge of 13.5nC at 4.5V V GS .
4. The diode for this design must handle a maximum DC
output current of 2A and be rated for a minimum reverse
voltage of V OUT , or 5V. A 25A, 15V diode from On Semi-
conductor (MBRB2515L) was chosen for its high power
dissipation capability.
5. The output capacitor usually consists of a lower valued,
low ESR ceramic.
6. The choice of an input capacitor for a boost converter
depends on the impedance of the source supply and the
amount of input ripple the converter will safely tolerate.
For this particular design two 22μF Taiyo Yuden ceramic
capacitors (JMK325BJ226MM) are required (the input
and return lead lengths are kept to a few inches). As
with the output node, check the input ripple with a single
oscilloscope probe connected across the input capacitor
terminals.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3872. These items are illustrated graphically in
the layout diagram in Figure 8. Check the following in
your layout:
1. The Schottky diode should be closely connected between
the output capacitor and the drain of the external MOSFET.
2. The input decoupling capacitor (0.1μF) should be con-
nected closely between V IN and GND.
3. The trace from SW to the switch point should be kept
short.
4. Keep the switching node NGATE away from sensitive
small signal nodes.
5. The V FB pin should connect directly to the feedback
resistors. The resistive divider R1 and R2 must be con-
nected between the (+) plate of C OUT and signal ground.
R ITH
IPRG
I TH
SW
RUN/SS
LTC3872
C ITH
V FB
GND
V IN
NGATE
C IN
C OUT
R1
R2
L1
D1
M1
V OUT
BOLD LINES INDICATE HIGH CURRENT PATHS
3872 F08
V IN
Figure 8. LTC3872 Layout Diagram (See PC Board Layout Checklist)
3872fc
For more information www.linear.com/LTC3872
15
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