参数资料
型号: LTC4065EDC#TRM
厂商: Linear Technology
文件页数: 15/16页
文件大小: 0K
描述: IC CHARGER BATT LI-ON 6-DFN
标准包装: 500
功能: 充电管理
电池化学: 锂离子(Li-Ion)
电源电压: 3.75 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-WFDFN 裸露焊盘
供应商设备封装: 6-DFN-EP(2x2)
包装: 带卷 (TR)
其它名称: LTC4065EDC-ND
LTC4065/LTC4065A
APPLICATIO S I FOR ATIO
Furthermore, the voltage at the PROG pin will change
proportionally with the charge current as discussed in the
Programming Charge Current section.
It is important to remember that LTC4065/LTC4065A
applications do not need to be designed for worst-case
thermal conditions since the IC will automatically reduce
power dissipation when the junction temperature reaches
approximately 115 ° C.
Board Layout Considerations
In order to deliver maximum charge current under all
conditions, it is critical that the exposed metal pad on the
backside of the LTC4065/LTC4065A package is soldered
to the PC board ground. Correctly soldered to a 2500mm 2
double-sided 1 oz. copper board the LTC4065/LTC4065A
has a thermal resistance of approximately 60 ° C/W. Failure
backside of the package and the copper board will result
in thermal resistances far greater than 60 ° C/W. As an
example, a correctly soldered LTC4065/LTC4065A can
deliver over 750mA to a battery from a 5V supply at room
temperature. Without a backside thermal connection, this
number could drop to less than 500mA.
V CC Bypass Capacitor
Many types of capacitors can be used for input bypassing;
however, caution must be exercised when using multi-
layer ceramic capacitors. Because of the self-resonant and
high Q characteristics of some types of ceramic capaci-
tors, high voltage transients can be generated under some
start-up conditions, such as connecting the charger input
to a live power source. For more information, refer to
Application Note 88.
to make thermal contact between the Exposed Pad on the
PACKAGE DESCRIPTIO
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703)
R = 0.115
TYP
0.38 ± 0.05
0.675 ± 0.05
0.56 ± 0.05
(2 SIDES)
4
6
3
1
2.50 ± 0.05
1.15 ± 0.05 0.61 ± 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
1.42 ± 0.05
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
2.00 ± 0.10
(4 SIDES)
0.75 ± 0.05
PIN 1
CHAMFER OF
EXPOSED PAD
(DC6) DFN 1103
0.25 ± 0.05
0.50 BSC
1.37 ± 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4065fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
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