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参数资料
| 型号： | LTC4150IMS#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/14页 |
| 文件大小： | 0K |
| 描述： | IC COUNTER/GAUGE GAS/BATT 10MSOP |
| 标准包装： | 2,500 |
| 功能： | 燃料，电量检测计/监控器 |
| 电池化学： | 锂离子，镍镉，镍氢 |
| 电源电压： | 2.7 V ~ 8.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
LTC4150
APPLICATIONS INFORMATION
INT , POL and CLR
INT asserts low each time the LTC4150 measures a unit
of charge. At the same time, POL is latched to indicate
the polarity of the charge unit. The integrator and counter
continue running, so the microcontroller must service and
clear the interrupt before another unit of charge accumu-
lates. Otherwise, one measurement will be lost. The time
available between interrupts is the reciprocal of
Equation 2:
1
Time per INT Assertion = (9)
G VF ? ? V SENSE ?
At 50mV full scale, the minimum time available is 596ms.
To be conservative and accommodate for small, unex-
pected excursions above the 50mV sense voltage limit, the
microcontroller should process the interrupt and polarity
information and clear INT within 500ms.
Toggling CLR low for at least 20μs resets INT high and
unlatches POL. Since the LTC4150’s integrator and counter
operate independently of the INT and POL latches, no
charge information is lost during the latched period or
while CLR is low. Charge/discharge information contin-
ues to accumulate during those intervals and accuracy
is unaffected.
Once cleared, INT idles in a high state and POL indicates
real-time polarity of the battery current. POL high indicates
charge ?owing into the battery and low indicates charge
?owing out. Indication of a polarity change requires at
least:
Interfacing to INT , POL, CLR and SHDN
The LTC4150 operates directly from the battery, while in
most cases the microcontroller supply comes from some
separate, regulated source. This poses no problem for INT
and POL because they are open-drain outputs and can
be pulled up to any voltage 9V or less, regardless of the
voltage applied to the LTC4150’s V DD .
CLR and SHDN inputs require special attention. To drive
them, the microcontroller or external logic must generate
a minimum logic high level of 1.9V. The maximum input
level for these pins is V DD + 0.3V. If the microcontroller’s
supply is more than this, resistive dividers must be used
on CLR and SHDN . The schematic in Figure 6 shows an
application with INT driving CLR and microcontroller V CC
> V DD . The resistive dividers on CLR and SHDN keep the
voltages at these pins within the LTC4150’s V DD range.
Choose R2 and R1 so that:
(R1 + R2) ≥ 50R L (12)
R 1
1 . 9 V ≤ V CC ≤ V DD ( Minimum ) (13)
R 1 + R 2
Equation 13 also applies to the selection of R3 and R4.
The minimum V DD is the lowest supply to the LTC4150
when the battery powering it is at its lowest discharged
voltage.
When the battery is removed in any application, the CLR
and SHDN inputs are unpredictable. INT and POL outputs
may be erratic and should be ignored until after the bat-
tery is replaced.
t POL =
2
G VF ? 1024 ? ? V SENSE ?
(10)
If desired, the simple logic of Figure 4 may be used to
derive separate charge and discharge pulse trains from
INT and POL.
where V SENSE is the smallest sense voltage magnitude
before and after the polarity change.
INT
CHARGE
Open-drain outputs POL and INT can sink I OL = 1.6mA
at V OL = 0.5V. The minimum pull-up resistance for these
pins should be:
LTC4150
CLR
POL
DISCHARGE
R L > (V CC – 0.5)/1.6mA
(11)
4150 F04
where V CC is the logic supply voltage. Because speed isn’t
an issue, pull-up resistors of 10k or higher are adequate.
Figure 4. Unravelling Polarity—
Separate Charge and Discharge Outputs
4150fc
9
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