参数资料
型号: LTC4214-2CMS
厂商: Linear Technology
文件页数: 22/32页
文件大小: 277K
描述: IC CTRLR HOTSWAP NEGVOLT 10MSOP
标准包装: 50
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: 6 V ~ 16 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
LTC4214-1/LTC4214-2
22
421412f
Figure 10. Undervoltage Timing (All Waveforms are Referenced to V
EE
)
APPLICATIO  S I FOR  ATIO
U
U
U
(40礎 + 8 " I
DRN
) current pull-up. As the load capacitor
nears full charge, load current begins to decline. At point
8, the load current falls and the SENSE voltage drops below
V
ACL
(t). The analog current limit loop shuts off and the
GATE pin ramps further. At time point 9, the SENSE voltage
drops below V
CB
 and the fault TIMER cycle ends, followed
by a 5礎 discharge cycle (cool off). When GATE ramps
past V
GATEH
 threshold at time point 10, PWRGD pulls low.
At time point 11, GATE reaches its maximum voltage as
determined by V
IN
.
Undervoltage Timing
In Figure 10 when the UV pin drops below V
UVHI
  V
UVHST
(time point 1), the LTC4214 shuts down with TIMER, SS
and GATE all pulling low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV recovers and clears V
UVHI
 (time point 2), an
initial timer cycle begins followed by a start-up cycle.
UV
TIMER
GATE
SENSE
SS
DRAIN
PWRGD
5礎
50礎
5礎
5礎
50礎
UV DROPS BELOW V
UVHI
  V
UVHST
. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
1
2
3 4 56    7   89
TIMER CLEARS V
TMRL
, CHECK GATE < V
GATEL
, SENSE < V
CB
 AND SS < 20 " V
OS
1011
4214 F10
UV CLEARS V
UVHI
, CHECK OV CONDITION, GATE < V
GATEL
, SENSE < V
CB
, SS < 20 " V
OS
 AND TIMER < V
TMRL
V
ACL
V
CB
40礎 + 8 " I
DRN
20 " V
OS
V
IN
  V
GATEH
V
DRNL
V
DRNCL
20 " (V
CB
 + V
OS
)
20 " (V
ACL
 + V
OS
)
V
GATEL
V
TMRL
V
TMRH
V
UVHI
V
UVHI
 
V
UVHST
GATE
START-UP
INITIAL TIMING
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