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| 型号： | LTC4214-2IMS#TR |
| 厂商： | Linear Technology |
| 文件页数： | 15/32页 |
| 文件大小： | 277K |
| 描述： | IC CONTROLLER HOTSWAP NEG 10MSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 6 V ~ 16 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
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LTC4214-1/LTC4214-2
15
421412f
MOSFET off. To handle this situation, the TIMER dis-
charges C
T
slowly with a 5礎 pull-down whenever the
SENSE voltage is less than 50mV. Therefore, any intermit-
tent overload with V
OUT
< 3V and an aggregate duty cycle
of 12.5% or more will eventually trip the circuit breaker
and shut down the LTC4214. Figure 4 shows the circuit
breaker response time in seconds normalized to 1礔 for
I
DRN
= 0礎. The asymmetric charging and discharging of
C
T
is a fair gauge of MOSFET heating.
The normalized circuit response time is estimated by
t
C F
I
D
T
DRN
( )
"
"
?/DIV>
=
+
(
)
[
]
3
40 8
5
(4)
pull-down cycles and three 5礎 pull-up cycles occur
between the 1.7V and 3V thresholds, creating a time
interval given by:
t
V C
A
SHUTDOWN
T
=
?/DIV>
7 1 3
5
" . "
(5)
At the 1.7V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
SOFT-START
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFETs SOA rating if powering up into an active load. If
SS floats, an internal current source ramps SS from 0V to
1.6V in about 220祍. Connecting an external capacitor C
SS
from SS to ground modifies the ramp to approximate an
RC response of:
V t V
e
SS
SS
t
R C
SS
SS
( )
"
"
H
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
1
(6)
An internal resistor divider (69.35k/3.65k) scales V
SS
(t)
down by 20 times to give the analog current limit thresh-
old:
V
t
V t
V
ACL
SS
OS
( )
( )
=
20
(7)
This allows the inrush current to be limited to V
ACL
(t)/R
S
.
The offset voltage, V
OS
(10mV), ensures C
SS
is sufficiently
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
APPLICATIO S I FOR ATIO
U
U
U
FAULT DUTY CYCLE (%)
0.1
1
10
100
0 10
40 50 60 70 80 90
0.01
20 30
100
4214 F04
=
3
[(40 + 8 " I
DRN
) " D 5]
t
C
T
(礔)
I
DRN
= 0礎
Figure 4. Circuit-Breaker Response Time
SHUTDOWN COOLING CYCLE
For the LTC4214-1 (latchoff version), TIMER latches high
with a 5礎 pull-up after the circuit breaker fault TIMER
reaches 3V. For the LTC4214-2 (automatic retry version),
a shutdown cooling cycle begins if TIMER reaches the 3V
threshold. TIMER starts with a 5礎 pull-down until it
reaches the 1.7V threshold. Then, the 5礎 pull-up turns
back on until TIMER reaches the 3V threshold. Four 5礎
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