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| 型号： | LTC4230CGN#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 24/36页 |
| 文件大小： | 384K |
| 描述： | IC CONTRLLR HOT SWAP TRPL 20SSOP |
| 标准包装： | 55 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 1.7 V ~ 16.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
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24
LTC4230
4230f
maximum rating for V
GS
is typically ?0V for standard
MOSFETs. However, the V
GS
maximum rating for logic-
level MOSFETs ranges from ?V to ?0V depending upon
the manufacturer and the specific part number. The
LTC4230s gate overdrive as a function of V
CC
is illustrated
in the Typical Performance curves. Logic-level MOSFETs
are recommended for low supply voltage applications and
standard MOSFETs can be used for applications where
supply voltage is greater than 4.75V.
Note that in some applications, the gate of the external
MOSFET can discharge faster than the output voltage
when the circuit breaker is tripped. This causes a negative
V
GS
voltage on the external MOSFET. Usually, the selected
external MOSFET should have a 盫
GS(MAX)
rating that is
higher than the operating input supply voltage to ensure
that the external MOSFET is not destroyed by a negative
V
GS
voltage. In addition, the 盫
GS(MAX)
rating of the
MOSFET must be higher than the gate overdrive voltage.
Lower 盫
GS(MAX)
rating MOSFETs can be used with the
LTC4230 if the GATEn overdrive is clamped to a lower
voltage. The circuit in Figure 13 illustrates the use of zener
diodes to clamp the LTC4230s GATEn overdrive signal if
lower voltage MOSFETs are used.
The R
DS(ON)
of the external pass transistor should be low
to make its drain-source voltage (V
DS
) a small percentage
of V
CC
. At a V
CC
= 2.5V, V
DS
+ V
RSENSE
= 0.1V yields 4%
error at the output voltage. This restricts the choice of
MOSFETs to very low R
DS(ON)
. At higher V
CC
voltages, the
V
DS
requirement can be relaxed in which case MOSFET
package dissipation (P
D
and T
J
) may limit the value of
R
DS(ON)
. Table 5 lists some power MOSFETs that can be
used with the LTC4230.
Power MOSFET junction temperature is dependent on four
parameters: current delivered to the load, I
LOAD
, R
DS(ON)
,
junction-to-ambient thermal resistance, ?/DIV>
JA
, and the maxi-
mum ambient temperature to which the circuit will be
exposed, T
A(MAX)
. For reliable circuit operation, the maxi-
mum junction temperature (T
J(MAX)
) for a power MOSFET
should not exceed the manufacturers recommended value.
This includes normal mode operation, start-up, current-
limit and autoretry mode in a fault condition. For a given
set of conditions, the junction temperature of a power
MOSFET is given by Equation 13:
MOSFET Junction Temperature,
T
J(MAX)
d (T
A(MAX)
+ ?/DIV>
JA
" P
D
)
(13)
where
P
D
= (I
LOAD
)
2
" R
DS(ON)
PCB layout techniques for optimal thermal management
of power MOSFET power dissipation help to keep device
?/DIV>
JA
as low as possible. See the section on PCB Layout
Considerations for more information.
V
CC
V
OUT
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
4230 F13
R
SENSE
R
G
200&
GATE
D1*
D2*
Q1
Figure 13. Optional Gate Clamp for Lower V
GS(MAX)
MOSFETs
USING STAGGERED PIN CONNECTORS
The LTC4230 can be used on either a printed circuit board
or on the backplane side of the connector, and examples
for both are shown in Figure 14. Printed circuit board edge
connectors with staggered pins are recommended as the
insertion and removal of circuit boards do sequence the
pin connections. Supply voltage and ground connections
on the printed circuit board should be wired to the edge
connectors long pins or blades. Control and status sig-
nals (like RESETn, FAULT and ON) passing through the
cards edge connector should be wired to short length pins
or blades.
APPLICATIO S I FOR ATIO
U
U
U
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