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| 型号： | LTC4230IGN#TR |
| 厂商： | Linear Technology |
| 文件页数： | 10/36页 |
| 文件大小： | 384K |
| 描述： | IC CONTRLLR HOT SWAP TRPL 20SSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 1.7 V ~ 16.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | LTC4230IGNTR |
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10
LTC4230
4230f
SENSE 2 (Pin 17): Circuit Breaker Sense Pin for Chan-
nel 2. With a sense resistor placed in the power path
between V
CC2
and SENSE 2, Channel 2s electronic circuit
breaker trips if the voltage across the sense resistor (V
CC2
V
SENSE2
) exceeds the thresholds set internally for SLOW
COMP2 and FAST COMP2, as shown in the Block Diagram.
The threshold for SLOW COMP2 is V
CB(SLOW)
= 50mV and
the electronic circuit breaker trips if the voltage across
R
SENSE2
exceeds 50mV for 10祍, or for the time delay
programmed by C
FILTER
. To adjust SLOW COMP2s delay,
please refer to the section on Adjusting SLOW COMPns
Response Time.
Under transient conditions where large step current
changes can and do occur over shorter periods of time, a
second (fast) comparator instead trips the electronic
circuit breaker. The threshold for FAST COMP2 is set at
V
CB(FAST)
= 150mV, and the circuit breaker trips if the
voltage across the R
SENSE2
exceeds 150mV for more than
500ns. FAST COMP2s delay is fixed in the LTC4230 and
cannot be adjusted. To disable Channel 2s electronic
circuit breaker, connect the V
CC2
and SENSE 2 pins
together.
GATE 2 (Pin 18): The output signal at this pin is the high
side gate drive for Channel 2s external N-channel FET
pass transistor. An internal charge pump produces a 4.5V
(minimum) to 18V (maximum) gate drive voltage for V
CC1
supply voltages from 2.7V to 16.5V, respectively.
As shown in the Block Diagram for each channel, an
internal charge pump supplies a 10礎 gate current and
sufficient gate voltage drive to the external FET. The
internal charge pump produces a minimum 4.5V gate
drive for V
CC1
< 4.75V. For V
CC1
> 4.75V, the minimum
gate voltage drive is 9V. For V
CC1
e 12V, the minimum gate
voltage drive is 7V which is set by an internal zener diode
clamp connected between the GATE 2 pin and GND.
RESET 2 (Pin 19): An open-drain N-channel device whose
source connects to GND (Pin 14). This pin pulls low if the
voltage at FB2 (Pin 20) falls below the FB2 threshold
(1.234V). This pin requires an external pull-up resistor to
V
OUT2
. If an undervoltage lockout condition occurs, the
RESET 2 pin pulls low independently of FB2 to prevent
false glitches.
FB2 (Pin 20): The FB2 (Feedback) pin is an input to the
FBCOMP2 comparator which monitors the V
CC2
output
supply voltage through an external resistor divider. If V
FB2
< 1.234V, RESET 2 pulls low. An internal glitch filter at
FBCOMP3s output prevents triggering a reset condition
due to negative voltage transients. If V
FB2
> 1.237V,
RESET 2 pin goes high after exiting undervoltage lockout.
PI FU CTIO S
U
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