参数资料
型号: LTC4251-1CS6#TRM
厂商: Linear Technology
文件页数: 11/24页
文件大小: 266K
描述: IC CTRLR HOTSWAP NEGVOLT SOT23-6
标准包装: 1
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: -36 V ~ -72 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: SOT-23-6 细型,TSOT-23-6
供应商设备封装: SOT-23-6
包装: 剪切带 (CT)
其它名称: LTC4251-1CS6
LTC4251-1CS6#TRMCT
LTC4251-1CS6-ND
LTC42511CS6
11
425112fd
LTC4251/LTC4251-1/
LTC4251-2
For more information www.linear.com/4251
SHUNT REGULATOR
A fast responding shunt regulator clamps the V
IN
 pin to
13V (V
Z
). Power is derived from 48RTN by an external
current limiting resistor, R
IN
. A 1礔 decoupling capacitor,
C
IN
 filters supply transients and contributes a short delay
at start-up.
To meet creepage requirements R
IN
 may be split into two
or more series connected units, such as two 5.1k or three
3.3k resistors. This introduces a wider total spacing than is
possible with a single component while at the same time
ballasting the potential across the gap under each resistor.
The LTC4251 is fundamentally a low voltage device that
operates with 48V as its reference ground. To further
protect against arc discharge into its pins, the area in and
around the LTC4251 and all associated components should
be free of any other planes such as chassis ground, return,
or secondary-side power and ground planes.
V
IN
 is rated handle 30mA within the thermal limits of the
package, and is tested to survive a 100祍, 100mA pulse. To
protect V
IN
 against damage from higher amplitude spikes,
clamp V
IN
 to V
EE
 with a 13V Zener diode. Star connect
V
EE
 and all V
EE
 referred components to the sense resistor
Kelvin terminal as illustrated in Figure 2, keeping trace
lengths between V
IN
, C
IN
, D
IN
 and V
EE
 as short as possible.
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
Internal circuitry monitors V
IN
 for undervoltage. The exact
thresholds are defined by V
LKO
 and its hysteresis, V
LKH
.
When V
IN
 rises above 9.2V (V
LKO
) the chip is enabled;
below 8.2V (V
LKO
-V
LKH
) it is disabled and GATE is pulled
low. The UVLO function at V
IN
 should not be confused with
the UV/OV pin. These are completely separate functions.
UV/OV COMPARATORS
Two hysteretic comparators for detecting under- and
overvoltage conditions, with the following thresholds,
monitor the dual function UV/OV pin:
UV turning on at V
UVHI
UV turning off at V
UVLO
APPLICATIONS INFORMATION
OV turning off at V
OVHI
OV turning on at V
OVLO
The UV and OV trip point ratio for LTC4251 is designed to
match the standard telecom operating range of 43V to 75V .
The LTC4251-2 implements a UV threshold of 43V only.
A divider (R1, R2) is used to scale the supply voltage. Using
R1 = 402k and R2 = 32.4k gives a typical operating range
of 43.2V to 74.4V . The under- and overvoltage shutdown
thresholds are then 39.2V and 82.5V . 1% divider resis-
tors are recommended to preserve threshold accuracy.
The same resistor values can be used for the LTC4251-2.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100礎, and
define an impedance at UV/OV of 30k. In most applications,
30k impedance coupled with 300mV UV hysteresis makes
the LTC4251/LTC4251-1/LTC4251-2 insensitive to noise. If
more noise immunity is desired, add a 1nF to 10nF filter
capacitor from UV/OV to V
EE
.
The UV and OV trip point thresholds for the LTC4251-1 are
designed to encompass the standard telecom operating
range of 36V to 72V .
A divider (R1, R2) is used to scale the supply voltage.
Using R1 = 442k and R2 = 34.8k gives a typical operating
range of 33.2V to 81V . The typical under- and overvoltage
shutdown thresholds are then 29.6V and 84.5V . 1% divider
resistors are recommended to preserve threshold accuracy.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100礎, and
define an impedance at UV/OV of 32k. In most applica-
tions, 32k impedance coupled with 260mV UV hysteresis
makes the LTC4251-1 insensitive to noise. If more noise
immunity is desired, add a 1nF to 10nF filter capacitor
from UV/OV to V
EE
.
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the three
remaining interlock conditions are met.
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