参数资料
型号: LTC4251-1IS6#TRM
厂商: Linear Technology
文件页数: 9/24页
文件大小: 266K
描述: IC CTRLR HOTSWAP NEGVOLT SOT23-6
标准包装: 500
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: -36 V ~ -72 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-6 细型,TSOT-23-6
供应商设备封装: SOT-23-6
包装: 带卷 (TR)
其它名称: LTC4251-1IS6
LTC4251-1IS6-ND
LTC42511IS6
9
425112fd
LTC4251/LTC4251-1/
LTC4251-2
For more information www.linear.com/4251
OPERATION
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient currents
from the power bus as they charge. The flow of current
damages the connector pins and glitches the power bus,
causing other boards in the system to reset. The LTC4251/
LTC4251-1/LTC4251-2 are designed to turn on a circuit
board supply in a controlled manner, allowing insertion or
removal without glitches or connector damage.
Initial Start-Up
The LTC4251/LTC4251-1/LTC4251-2 reside on a removable
circuit board and control the path between the connector
and load or power conversion circuitry with an external
MOSFET switch (see Figure 1). Both inrush control and
short-circuit protection are provided by the MOSFET .
A detailed schematic is shown in Figure 2. 48V and
48RTN receive power through the longest connector pins,
and are the first to connect when the board is inserted.
The GATE pin holds the MOSFET off during this time. UV/
OV determines whether or not the MOSFET should be
turned on based upon internal, high accuracy thresholds
and an external divider. UV/OV does double duty by also
monitoring whether or not the connector is seated. The top
of the divider detects 48RTN by way of a short connector
pin that is the last to mate during the insertion sequence.
Interlock Conditions
A start-up sequence commences once five initial interlock
conditions are met:
1. The input voltage V
IN
 exceeds 9.2V (V
LKO
)
2. The voltage at UV/OV falls within the range of V
UVHI
 to
V
OVLO
 (UV > V
UVHI
, LTC4251-2)
3. The (SENSE  V
EE
) voltage is <50mV (V
CB
)
4. The voltage on the timer capacitor (C
T
) is less than 1V
(V
TMRL
)
5. GATE is less than 0.5V (V
GATEL
)
The first two conditions are continuously monitored and
the latter three are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
TIMER begins the start-up sequence by sourcing 5.8礎
into C
T
. If V
IN
 or UV/OV falls out of range, the start-up
cycle stops and TIMER discharges C
T
 to less than 1V ,
then waits until the aforementioned conditions are once
again met. If C
T
 successfully charges to 4V , TIMER pulls
low and GATE is released. GATE sources 58礎 (I
GATE
),
charging the MOSFET gate and associated capacitance.
 
Note that for simplicity, the following assumptions are made in the text. Firstly, UV/OV also means the UV
pin of the LTC4251-2. Secondly, all overvoltage conditions and references to OV, V
OVHI
 and V
OVLO
 do not apply to the LTC4251-2 as the
OV comparator in this part is disabled.
425112 F01
LTC4251
C
LOAD
ISOLATED
DC/DC
CONVERTER
MODULE
LOW
VOLTAGE
CIRCUITRY
+
+


PLUG-IN BOARD
BACKPLANE
48RTN
48V
+
3
4
1
2
425112 F02
48RTN
48V
UV/OV
TIMER
V
EE
V
IN
SENSE    GATE
LTC4251
R1
402k
1%
R2
32.4k
1%
C
T
150nF
C
C
18nF
R
S
20m
Q1
IRF530S
R
C
10
R
IN
10k
500mW
C1
10nF
C
IN
1礔
D
IN
 
DDZ13B**
C
L
100礔
TYP
LONG
LONG
SHORT
**DIODES, INC.
 RECOMMENDED FOR HARSH ENVIRONMENTS
+
Figure 1. Basic LTC4251 Hot Swap Topology
Figure 2. 48V, 2.5A Hot Swap Controller
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