参数资料
型号: LTC4251-2CS6#TRM
厂商: Linear Technology
文件页数: 15/24页
文件大小: 266K
描述: IC CTRLR HOTSWP NEG VOLT SOT23-6
标准包装: 500
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: -43V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: SOT-23-6 细型,TSOT-23-6
供应商设备封装: SOT-23-6
包装: 带卷 (TR)
其它名称: LTC4251-2CS6
LTC4251-2CS6-ND
15
425112fd
LTC4251/LTC4251-1/
LTC4251-2
For more information www.linear.com/4251
FREQUENCY COMPENSATION
The LTC4251/LTC4251-1/LTC4251-2 typical frequency
compensation network for the analog current limit loop
is a series R
C
 (10? and C
C
 connected to V
EE
. Figure 5
depicts the relationship between the compensation ca-
pacitor C
C
 and the MOSFETs C
ISS
. The line in Figure 5
is used to select a starting value for C
C
 based upon the
MOSFETs C
ISS
 specification. Optimized values for C
C
 are
shown for several popular MOSFETs. Differences in the
optimized value of C
C
 versus the starting value are small.
Nevertheless, compensation values should be verified by
board level short-circuit testing.
As seen in Figure 4 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramatically
owing to series inductance. If this voltage avalanches the
MOSFET , current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
resistor. PCB layout should be balanced and symmetrical to
minimize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
APPLICATIONS INFORMATION
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the V
EE
 and
SENSE pins are strongly recommended. The drawing in
Figure 6 illustrates the correct way of making connections
between the LTC4251/LTC4251-1/LTC4251-2 and the sense
TIMING WAVEFORMS
System Power-Up
Figure 7 details the timing waveforms for a typical
power-up sequence in the case where a board is already
installed in the backplane and system power is applied
abruptly. At time point 1, the supply ramps up, together
with UV/OV and V
OUT
. V
IN
 follows at a slower rate as set
by the V
IN
 bypass capacitor. At time point 2, V
IN
 exceeds
V
LKO
 and the internal logic checks for V
UVHI
 < UV/OV <
V
OVLO
, TIMER < V
TMRL
, GATE < V
GATEL
 and SENSE < V
CB
.
When all conditions are met, an initial timing cycle starts
and the TIMER capacitor is charged by a 5.8礎 current
source pull-up. At time point 3, TIMER reaches the V
TMRH
 
threshold and the initial timing cycle terminates. The
TIMER capacitor is then quickly discharged. At time point
4, the V
TMRL
 threshold is reached and the conditions of
GATE < V
GATEL
 and SENSE < V
CB
 must be satisfied before
a start-up cycle is allowed to begin. GATE sources 58礎
into the external MOSFET gate and compensation network.
When the GATE voltage reaches the MOSFETs threshold,
current begins flowing into the load capacitor. At time
point 5, the SENSE voltage (V
SENSE
 V
EE
 ) reaches the V
CB
 
threshold and activates the TIMER. The TIMER capacitor
MOSFET C
ISS
 (pF)
425112 F05
60
50
40
30
20
10
0
0
2000
4000
6000
8000
IRF530
IRF540
IRF740
IRF3710
MTY100N10E
Figure 5. Recommended Compensation
Capacitor C
C
 vs MOSFET C
ISS
W
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO 48V BACKPLANE
SENSE RESISTOR
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
TO
SENSE
TO
V
EE
425112 F06
Figure 6. Making PCB Connections to the Sense Resistor
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