参数资料
型号: LTC4252-2IMS#PBF
厂商: Linear Technology
文件页数: 9/36页
文件大小: 328K
描述: IC CNTRLR HOTSWAP NEGVOLT 10MSOP
标准包装: 50
类型: 热交换控制器
应用: 通用
内部开关:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
9
425212fe
For more information www.linear.com/LTC4252-1
pin FuncTions
V
IN
(Pin 1/Pin 1): Positive Supply Input. Connect this 
pin to the positive side of the supply through a dropping
resistor. A shunt regulator clamps V
IN
 at 13V . An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the V
IN
 pin is greater than V
LKO
, overriding UV and OV . If
UV is high, OV is low and V
IN
 comes out of UVLO, TIMER
starts an initial timing cycle before initiating a GATE ramp-
up. If V
IN
 drops below approximately 8.2V , GATE pulls low
immediately.
PWRGD (Pin 2/Not Available): Power Good Status Output 
(MS only). At start-up, PWRGD latches low if DRAIN is
below 2.385V and GATE is within 2.8V of V
IN
. PWRGD
status is reset by UV , V
IN
 (UVLO) or a circuit breaker fault
timeout. This pin is internally pulled high by a 58礎 cur-
rent source.
SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp 
inrush current during start up, thereby effecting control
over di/dt. A 20x attenuated version of the SS pin voltage
is presented to the current limit amplifier. This attenuated
voltage limits the MOSFETs drain current through the sense
resistor during the soft-start current limiting. At the begin-
ning of a start-up cycle, the SS capacitor (C
SS
) is ramped
by a 22礎 (28礎 for the LTC4252A) current source. The
GATE pin is held low until SS exceeds 20 " V
OS
 = 0.2V .
SS is internally shunted by a 100k resistor (R
SS
) which
limits the SS pin voltage to 2.2V (50k resistor and 1.4V
for the LTC4252A). This corresponds to an analog current
limit SENSE voltage of 100mV (60mV for the LTC4252A). If
the SS capacitor is omitted, the SS pin ramps up in about
180祍. The SS pin is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense 
Pin. Load current is monitored by a sense resistor R
S
 con-
nected between
 
SENSE and V
EE
, and controlled in three
steps.
 
If SENSE exceeds V
CB
 (50mV), the circuit breaker
comparator activates a (230礎 + 8 " I
DRN
) TIMER pull-up
current. If SENSE exceeds V
ACL
, the analog current limit
amplifier pulls GATE down to regulate the MOSFET current
at V
ACL
/R
S
. In the event of a catastrophic short-circuit,
SENSE may overshoot. If SENSE reaches V
FCL
 (200mV),
the fast current limit comparator pulls GATE low with a
strong pull-down. To disable the circuit breaker and cur-
rent limit functions, connect SENSE
 
to V
EE
.
(MS/MS8)
Typical perForMance characTerisTics
I
PGH
 vs Temperature
t
SS
 vs Temperature
t
PLLUG
 and t
PHLOG
 
vs Temperature
TEMPERATURE (癈)
55 35 15  5   25   45   65   85  105 125
425212 G38
62
61
60
59
58
57
56
55
V
PWRGD
 = 0V
(MS ONLY)
TEMPERATURE (癈)
55 35 15  5   25   45   65   85  105 125
425212 G27
220
210
200
190
180
170
160
150
SS PIN FLOATING,
V
SS
 RAMPS FROM 0.2V TO 2V
TEMPERATURE (癈)
55
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
15
25   45
125
35
5
65   85  105
t
PLLUG
t
PHLOG
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