参数资料
型号: LTC4252A-1CMS
厂商: Linear Technology
文件页数: 14/36页
文件大小: 328K
描述: IC CTRLR HOTSWAP NEG VOLT 10MSOP
标准包装: 50
类型: 热交换控制器
应用: 通用
内部开关:
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
14
425212fe
For more information www.linear.com/LTC4252-1
SHUNT REGULATOR
A fast responding shunt regulator clamps the V
IN
 pin to 13V
(VZ). Power is derived from 48RTN by an external current
limiting resistor, R
IN
. A 1礔 decoupling capacitor, C
IN
 filters
supply transients and contributes a short delay at start-up.
To meet creepage requirements R
IN
 may be split into two or
more series connected units. This introduces a wider total
spacing than is possible with a single component while at
the same time ballasting the potential across the gap under
each resistor. The LTC4252 is fundamentally a low voltage
device that operates with 48V as its reference ground. To
further protect against arc discharge into its pins, the area
in and around the LTC4252 and all associated components
should be free of any other planes such as chasis ground,
return, or secondary-side power and ground planes.
V
IN
 may be biased with additional current up to 30mA to
accomodate external loading such as the PWRGD opto-
coupler shown in Figure 23. As an alternative to running
higher current, simply buffer V
IN
 with an emitter follower
as shown in Figure 3. Another method shown in Figure
19 cascodes the PWRGD output.
V
IN
 is rated handle 30mA within the thermal limits of the
package, and is tested to survive a 100祍, 100mA pulse. To
protect V
IN
 against damage from higher amplitude spikes,
clamp V
IN
 to V
EE
 with a 13V Zener diode. Star connect
V
EE
 and all V
EE
-referred components to the sense resistor
applicaTions inForMaTion
Kelvin terminal as illustrated in Figure 3, keeping trace
lengths between V
IN
, C
IN
, D
IN
 and V
EE
 as short as possible.
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
A hysteretic comparator, UVLO, monitors V
IN
 for undervolt-
age. The thresholds are defined by V
LKO
 and its hysteresis,
V
LKH
. When V
IN
 rises above V
LKO
 the chip is enabled; below
(V
LKO
  V
LKH
) it is disabled and GATE is pulled low. The
UVLO function at V
IN
 should not be confused with the
UV/OV pin(s). These are completely separate functions.
UV/OV COMPARATORS (LTC4252)
An UV hysteretic comparator detects undervoltage condi-
tions at the UV pin, with the following thresholds:
   UV low-to-high (V
UVHI
) = 3.225V
   UV high-to-low (V
UVLO
) = 2.925V
An OV hysteretic comparator detects overvoltage condi-
tions at the OV pin, with the following thresholds:
   OV low-to-high (V
OVHI
) = 6.150V
   OV high-to-low (V
OVLO
) = 5.550V
The UV and OV trip point ratio is designed to match the
standard telecom operating range of 43V to 82V when con-
nected together as in the typical application. A divider (R1,
R2) is used to scale the supply voltage. Using R1 = 402k
425212 F03
48RTN
UV
OV
V
EE
V
IN
SENSE
SS
TIMER
GATE
PWRGD
DRAIN
LTC4252-1
R1
432k
1%
R3
38.3k
1%
R2
4.75k
1%
C
T
330nF
C
SS
68nF
C
C
18nF
48V
R
S
0.02
Q1
IRF530S
R
C
10
R5
2.2k
Q2
R
IN
10k
1/2W
1
9
8
10
3
2
7
6
4
5
C2
10nF
C
IN
1礔
C
L
100礔
48RTN
(SHORT PIN)
+
R
D
 1M
LOAD
EN
R4
22k
*
* M0C207
Q2: MMBT5551LT1
**DIODES, INC
 
RECOMMENDED FOR HARSH ENVIRONMENTS
D
IN
 
DDZ13B
**
Figure 3. 48V/2.5A Application with Different Input Operating Range
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