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| 型号： | LTC4253IGN#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/34页 |
| 文件大小： | 383K |
| 描述： | IC HOT SWAP CONTRLR -48V 16-SSOP |
| 标准包装： | 100 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 11.2 V ~ 14.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 管件 |
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LTC4253/LTC4253A
16
425353aff
For more information www.linear.com/4253
APPLICATIONS INFORMATION
The separate UV and OV pins can be used for wider op-
erating range such as 35.6V to 76.3V range as shown in
Figure 2. Other combinations are possible with different
resistors arrangement.
UV/OV COMPARATORS (LTC4253A)
A UV hysteretic comparator detects undervoltage condi-
tions at the UV pin, with the following thresholds:
UV low-to-high (V
UV
) = 3.08V
UV high-to-low (V
UV
V
UVHST
) = 2.756V
An OV hysteretic comparator detects overvoltage condi-
tions at the OV pin, with the following thresholds:
OV low-to-high (V
OV
) = 5.09V
OV high-to-low (V
OV
V
OVHST
) = 4.988V
The UV and OV trip point ratio is designed to match the
standard telecom operating range of 43V to 71V when
connected together as in Figure 3. A divider (R1, R2) is
used to scale the supply voltage. Using R1 = 392k and R2
= 30.1k gives a typical operating range of 43.2V to 71.4V .
The undervoltage shutdown and overvoltage recovery
thresholds are then 38.6V and 69.9V . 1% divider resistors
are recommended to preserve threshold accuracy.
The R1-R2 divider values shown in Figure 3 set a stand-
ing current of slightly more than 100礎 and define an
impedance at UV/OV of 28k? In most applications, 28k?
impedance coupled with 324mV UV hysteresis makes
the LTC4253A insensitive to noise. If more noise im-
munity is desired, add a 1nF to 10nF filter capacitor from
UV/OV to V
EE
.
The UV and OV pins can also be used for a wider operating
range by adding a resistor between UV and OV as shown
in Figure 2 for the LTC4253. Other combinations are pos-
sible with different resistor arrangements.
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the other
interlock conditions are met. A high-to-low transition in
the UV comparator immediately shuts down the LTC4253/
LTC4253A, pulls the MOSFET gate low and resets the three
latched PWRGD signals high.
An overvoltage condition is detected by the OV compara-
tor and pulls GATE low, thereby shutting down the load,
but it will not reset the circuit breaker TIMER and PWRGD
flags. Returning from the overvoltage condition will
restart the GATE pin if all the interlock conditions except
TIMER are met. Only during the initial timing cycle does
OV condition have an effect of resetting TIMER.
DRAIN
Connecting an external resistor, R
D
, to this dual function
DRAIN pin allows V
OUT
(MOSFET drain-source voltage
drop) sensing without it being damaged by large voltage
transients. Below 5V , negligible pin leakage allows a DRAIN
low comparator to detect V
OUT
less than 2.39V (V
DRNL
).
This, together with the GATE low comparator, sets the
PWRGD flag.
When V
OUT
> V
DRNCL
, the DRAIN pin is clamped at V
DRNCL
and the current flowing in R
D
is given by:
I
DRN
H
V
OUT
V
DRNCL
R
D
(1)
This current is scaled up 8 times during a circuit breaker
fault before being added to the nominal 200礎. This ac-
celerates the fault TIMER pull-up when the MOSFETs
drain-source voltage exceeds V
DRNCL
and effectively
shortens the MOSFET heating duration.
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