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参数资料
型号： LTC4261CGN#PBF
厂商： Linear Technology
文件页数： 8/34页
文件大小： 361K
描述： IC CTRLR HOTSWAP W/ADC 28-SSOP
标准包装： 49
类型： 热交换控制器
应用： 通用
内部开关： 无
电源电压： 9 V ~ 11.2 V
工作温度： 0°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 28-SSOP（0.154"，3.90mm 宽）
供应商设备封装： 28-SSOP
包装： 管件
产品目录页面： 1342 (CN2011-ZH PDF)
LTC4261/LTC4261-2
8
42612fc
ADIN (Pin 23/Pin 16): ADC Input. A voltage between 0V 
and 2.56V applied to this pin is measured by the on-chip
ADC. Tie to V
EE
 if unused.
ADIN2 (Pin 10/NA): Second ADC Input. Not available on 
QFN package.
ADR0, ADR1 (Pins 24, 25/Pins 17, 18): Serial Bus Ad-
dress Inputs. Tying these pins to V
EE
, OPEN or INTV
CC
 
configures one of nine possible addresses. See Table 1
in Applications Information.
ALERT (Pin 3/Pin 24): Fault Alert Output. Open-drain logic 
output that pulls to V
EE
 when a fault occurs to alert the host
controller. A fault alert is enabled by the ALERT register.
See Applications Information. Connect to V
EE
 if unused.
DRAIN (Pin 16/Pin 11): Drain Sense Input. Connect an 
external 1M resistor between this pin and the drain terminal
(V
OUT
) of the N-channel FET . When the DRAIN pin volt-
age is less than 1.77V and the GATE pin voltage is above
V
Z
 1.2V the power good outputs are asserted after a
delay. The voltage at this pin is internally clamped to 4V .
EN (Pin 26/Pin 19): Device Enable Input. Pull low to enable 
the N-channel FET to turn-on after a start-up debounce
delay set by the TMR pin. When this pin is pulled high, the
FET is off. Transitions on this pin will be recorded in the
FAULT register. A high-to-low transition activates the logic
to read the state of the ON pin and clear faults. Requires
external pull-up. Debouncing with an external capacitor
is recommended when used to monitor board present.
Connect to V
EE
 if unused.
Exposed Pad (Pin 25, QFN Only): Exposed Pad may be 
left open or connected to device ground (V
EE
).
FLTIN (Pin 22/NA): General Purpose Fault Input. If this 
pin pulls low, the FAULT register bit B7 is latched to 1.
This pin is used to sense an external fault condition and
its status does not affect the FET control functions of the
LTC4261. Not available on the QFN package. Connect to
INTV
CC
 if unused.
GATE (Pin 15/Pin 10): N-Channel FET Gate Drive Output.
This pin is pulled up by an internal current source I
GATE
 
(11.5礎 when the SS pin reaches its clamping voltage).
GATE stays low until V
IN
 and INTV
CC
 cross the UVLO
thresholds, UV and OV conditions are satisified and an
adjustable timer delay expires. During turn-off, caused by
faults or undervoltage lockout (V
IN
 or INTV
CC
), a 110mA
pull-down current between GATE and V
EE
 is activated.
INTV
CC
 (Pin 7/Pin 4): Low Voltage (5V) Supply Output. 
This is the output of the internal linear regulator with an
internal UVLO threshold of 4.25V . This voltage powers up
the data converter and logic control circuitry. Bypass this
pin with a 0.1礔 capacitor to V
EE
.
ON (Pin 2/Pin 23): On Control Input. A rising edge turns 
on the external N-channel FET while a falling edge turns it
off. This pin is also used to configure the state of the FET
ON register bit D3 in the CONTROL register (and hence
the external FET) at power-up. For example if the ON pin
is tied high, then the register bit D3 goes high one timer
cycle after power-up. Likewise, if the ON pin is tied low, then
the device remains off after power-up until the register bit
D3 is set high using the I
2
C bus. A high-to-low transition
on this pin clears faults.
OV (Pin 11/Pin 7): Overvoltage Detection Input. Connect 
this pin to an external resistive divider from V
EE
. If the
voltage at the pin rises above 1.77V , the N-channel FET is
turned off. The overvoltage condition does not affect the
status of the power good outputs. On the QFN package,
this pin is also measured by the on-chip ADC. Connect
to V
EE
 if unused.
PG (Pin 27/Pin 20): Power Good Status Output. This open-
drain pin pulls low and stays latched a timer delay after
the FET is on (when GATE reaches V
Z
  1.2V and DRAIN
is within 1.77V of V
EE
). The power good output is reset
in all GATE pull-down events except an overvoltage fault.
Connect to V
EE
 if unused.
PIN FUNCTIONS (SSOP/QFN) 
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LTC4261CUFD 功能描述:IC CTRLR HOTSWAP W/ADC 24-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF)
LTC4261CUFD#PBF 功能描述:IC CTRLR HOTSWAP W/ADC 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF)
LTC4261CUFD#TR 功能描述:IC CTRLR HOTSWAP W/ADC 24-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF)
LTC4261CUFD#TRPBF 功能描述:IC CTRLR HOTSWAP W/ADC 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 热交换 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:119 系列:- 类型:热交换控制器 应用:通用型，PCI Express? 内部开关:无 电流限制:- 电源电压:3.3V，12V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:80-TQFP 供应商设备封装:80-TQFP（12x12） 包装:托盘 产品目录页面:1423 (CN2011-ZH PDF)
LTC4261CUFD-2 制造商:LINER 制造商全称:Linear Technology 功能描述:Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring
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