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参数资料
| 型号： | LTC4261IUFD-2#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 18/34页 |
| 文件大小： | 361K |
| 描述： | IC CTRLR HOTSWAP W/ADC 24-QFN |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 9 V ~ 11.2 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（5x4） |
| 包装： | 带卷 (TR) |
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LTC4261/LTC4261-2
18
42612fc
Figure 6. Overcurrent Fault and Auto-Retry
In the case of a low impedance short circuit on the load
side or an input step during battery replacement, current
overshoot is inevitable. A fast SENSE comparator with a
threshold of 250mV detects the overshoot and immedi-
ately pulls GATE low. Once the SENSE voltage drops to
50mV, the current limit loop takes over and servos the
current as previously described. If the short-circuit con-
dition lasts longer than 530祍, the FET is shut down and
the overcurrent fault is registered.
In the case of an input step, after an internal clamp pulls the
RAMP pin down to 1.1V, the inrush control circuit takes
over and the current limit loop is disengaged before the
circuit breaker timer expires. From this point on, the device
works as in the initial start-up: V
OUT
is ramped down at the
rate set by I
RAMP
and C
R
followed by GATE pull-up. The
power good signals on the PG and PGIO pins, the TMR
pin, and the SS pin are not interrupted through the input
step sequence. The waveform in Figure 7 shows how the
LTC4261/LTC4261-2 responds to an input step.
Note that the current limit threshold should be set
sufficiently high to accommodate the sum of the load
current and the inrush current to avoid engagement of
the current limit loop in the event of an input step. The
maximum value of the inrush current is given by:
I
INRUSH
d 0.8
45mV
R
S
I
LOAD
where the 0.8 factor is used as a worst case margin com-
bined with the minumum threshold (45mV).
The active current limit circuit is compensated using the
capacitor C
G
with a series resistor R
G
(10W) connected
between GATE and V
EE
, as shown in Figure 1. The sug-
gested value for C
G
is 50nF. This value should work for
most pass transistors (Q1).
Overvoltage Fault
An overvoltage fault occurs when the OV pin rises above
its 1.77V threshold. This shuts off the pass transistor
immediately, sets the overvoltage present bit A0 and
the overvoltage fault bit B0, and pulls the SS pin down.
Note that the power good signals are not affected by the
overvoltage fault. If the OV pin subsequently falls back
below the threshold, the pass transistor will be allowed
to turn on again immediately (without delay) unless the
APPLICATIONS INFORMATION
TMR
SS
GATE
V
OUT
SENSE
PG
PGIO
OC COOLING DELAY
PWRGD1
DELAY
4x
2x
V
Z
1.2V
1.77V
INRUSH
PWRGD2
DELAY
2x
50mV
530祍
42612 F06
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