LTC4267-1
25
42671f
In a nonisolated design, the LTC4267-1 incorporates an
internal error amplier where the ITH/RUN pin serves as
a compensation point. In a similar manner, a series RC
network can be connected from ITH/RUN to PGND as
shown in Figure 15. CC and RZ are chosen for optimum
load and line transient response.
Auxiliary Power Source
In some applications, it may be desirable to power the
PD from an auxiliary power source such as a wall trans-
former. The auxiliary power can be injected into the PD
at several locations and various trade-offs exist. Power
can be injected at the 3.3V or 5V output of the isolated
power supply with the use of a diode ORing circuit. This
method accesses the internal circuits of the PD after the
isolation barrier and therefore meets the 802.3af isola-
tion safety requirements for the wall transformer jack on
the PD. Power can also be injected into the PD interface
portion of the LTC4267-1. In this case, it is necessary to
ensure the user cannot access the terminals of the wall
transformer jack on the PD since this would compromise
the 802.3af isolation safety requirements.
Figure 16 demonstrates three methods of diode ORing
external power into a PD. Option 1 inserts power before
the LTC4267-1 interface controller while options 2 and
3 bypass the LTC4267-1 interface controller section and
power the switching regulator directly.
If power is inserted before the LTC4267-1 interface con-
troller, it is necessary for the wall transformer to exceed
the LTC4267-1 UVLO turn-on requirement and include a
transient voltage suppressor (TVS) to limit the maximum
voltage to 57V. This option provides input current limit
for the transformer, provides a valid power good signal,
and simplies power priority issues. As long as the wall
transformer applies power to the PD before the PSE, it
will take priority and the PSE will not power up the PD
because the wall power will corrupt the 25k signature. If
the PSE is already powering the PD, the wall transformer
power will be in parallel with the PSE. In this case, prior-
ity will be given to the higher supply voltage. If the wall
transformer voltage is higher, the PSE should remove the
line voltage since no current will be drawn from the PSE.
On the other hand, if the wall transformer voltage is lower,
the PSE will continue to supply power to the PD and the
wall transformer will not be used. Proper operation should
occur in either scenario.
APPLICATIO S I FOR ATIO
WU
UU
Figure 15. Main Loop Compensation for a Nonisolated Design
Selecting the Switching Transistor
With the N-channel power MOSFET driving the primary of
the transformer, the inductance will cause the drain of the
MOSFET to traverse twice the voltage across VPORTP and
PGND. The LTC4267-1 operates with a maximum supply
of – 57V; thus the MOSFET must be rated to handle 114V
or more with sufcient design margin. Typical transis-
tors have 150V ratings while some manufacturers have
developed 120V rated MOSFETs specically for Power-
over-Ethernet applications.
The NGATE pin of the LTC4267-1 drives the gate of the
N-channel MOSFET. NGATE will traverse a rail-to-rail volt-
age from PGND to PVCC. The designer must ensure the
MOSFET provides a low “ON” resistance when switched
to PVCC as well as ensure the gate of the MOSFET can
handle the PVCC supply voltage.
For high efciency applications, select an N-channel
MOSFET with low total gate charge. The lower total gate
charge improves the efciency of the NGATE drive circuit
and minimizes the switching current needed to charge
and discharge the gate.