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参数资料
| 型号： | LTC4274AIUHF-1#TRPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PQCC38 |
| 封装： | 7 X 5 MM, LEAD FREE, PLASTIC, MO-220WHKD, QFN-38 |
| 文件页数： | 15/28页 |
| 文件大小： | 313K |
| 代理商： | LTC4274AIUHF-1#TRPBF |
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LTC4274A/LTC4274C
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ApplicAtions inForMAtion
The LTC4274A/LTC4274C will support current levels well
beyond the maximum values in the 802.3at specification.
The shaded areas in Table 6 indicate settings that may
require a larger external MOSFET, additional heat sinking,
or enabling tLIM.
MOSFET Fault Detection
The LTC4274A/LTC4274C PSE port is designed to toler-
ate significant levels of abuse, but in extreme cases it is
possible for the external MOSFET to be damaged. A failed
MOSFET may short source to drain, which will make the
port appear to be on when it should be off; this condition
may also cause the sense resistor to fuse open, turning
off the port but causing the LTC4274A/LTC4274C SENSE
pin to rise to an abnormally high voltage. A failed MOSFET
may also short from gate to drain, causing the LTC4274A/
LTC4274C GATE pin to rise to an abnormally high voltage.
The LTC4274A/LTC4274C OUT, SENSE and GATE pins are
designed to tolerate up to 80V faults without damage.
IftheLTC4274A/LTC4274Cseesanyoftheseconditionsfor
more than 180μs, it disables all port functionality, reduces
the gate drive pull-down current for the port and reports
a FET Bad fault. This is typically a permanent fault, but
the host can attempt to recover by resetting the port, or
by resetting the entire chip if a port reset fails to clear the
fault. If the MOSFET is in fact bad, the fault will quickly
return, and the port will disable itself again.
An open or missing MOSFET will not trigger a FET Bad
fault,butwillcauseatSTARTfaultiftheLTC4274A/LTC4274C
attempts to turn on the port.
Voltage and Current Readback
The LTC4274A/LTC4274C measures the output voltage
and current at the port with an internal A/D converter. Port
data is only valid when the port power is on. The converter
has two modes:
Slowmode:14samplespersecond,14.5bitsresolution
Fastmode:440samplespersecond,9.5bitsresolution
Infastmode,theleastsignificant5bitsofthelowerbyteare
zeroes so that bit scaling is the same in both modes.
Disconnect
The LTC4274A/LTC4274C monitors the port to make sure
that the PD continues to draw the minimum specified
current. A disconnect timer counts up whenever port
current is below 7.5mA (typ), indicating that the PD has
been disconnected. If the tDIS timer expires, the port will
be turned off and the disconnect bit in the fault event reg-
ister will be set. If the current returns before the tDIS timer
runs out, the timer resets and will start counting from the
beginning if the undercurrent condition returns. As long
as the PD exceeds the minimum current level more often
than tDIS, it will stay powered.
Although not recommended, the DC disconnect feature
can be disabled by clearing the DC Disconnect Enable
bit. Note that this defeats the protection mechanisms
built into the IEEE spec, since a powered port will stay
powered after the PD is removed. If the still-powered port
is subsequently connected to a non-PoE data device, the
device may be damaged.
The LTC4274A/LTC4274C does not include AC discon-
nect circuitry, but includes an AC Disconnect Enable bit
to maintain compatibility with the LTC4259A. If the AC
Disconnect Enable bit is set, DC disconnect will be used.
Shutdown Pin
The LTC4274A/LTC4274C includes a hardware SHDN pin.
When the SHDN pin is pulled to DGND, the port will be
shut off immediately. The port remains shut down until
re-enabled via I2C or a device reset in AUTO pin mode.
Masked Shutdown
The LTC4274A/LTC4274C provides a low latency port
shedding feature to quickly reduce the system load when
required. By allowing a pre-determined set of ports to
be turned off, the current on an overloaded main power
supply can be reduced rapidly while keeping high priority
devices powered. Each port can be configured to high or
low priority; all low-priority ports will shut down within
6.5μs after the MSD pin is pulled low. If a port is turned off
via MSD, the corresponding Detection and Classification
Enable bits are cleared, so the port will remain off until
the host explicitly re-enables detection.
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