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参数资料
| 型号： | LTC4303IDD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/12页 |
| 文件大小： | 549K |
| 描述： | IC BUS BUFFER I2C 8-DFN |
| 产品培训模块： | LTC4310 - Hot-Swappable I²C Isolators |
| 标准包装： | 121 |
| 类型： | 热交换开关 |
| 应用： | 通用型缓冲器/总线扩展器 |
| 内部开关： | 是 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 供应商设备封装： | 8-DFN-EP（3x3） |
| 包装： | 管件 |
LTC4303
6
4303fb
Start-Up
When the LTC4303 rst receives power on its V
CC
pin,
either during power up or live insertion, it starts in an under
voltage lockout (UVLO) state, ignoring any activity on the
SDA or SCL pins until V
CC
rises above 2.5V (typical).
During this time, the precharge circuitry is active and
forces 1V through 200k nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged
into a live backplane, the voltage on the backplane SDA
and SCL busses may be anywhere between 0V and V
CC
.
Precharging the SCL and SDA pins to 1V minimizes the
worst-case voltage differential these pins will see at the
moment of connection, therefore minimizing the amount
of disturbance caused by the I/O card.
Once the LTC4303 comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the input side to indicate the
completion of a data transaction. When either one occurs,
the part also veri es that both the SDAOUT and SCLOUT
voltages are high. When all of these conditions are met,
the input-to-output connection circuitry is activated, join-
ing the SDA and SCL busses on the I/O card with those
on the backplane and READY goes high.
Connection Circuitry
Once the connection circuitry is activated, the functionality
of the SDAIN and SDAOUT pins is identical. A low forced
on either pin at any time results in both pin voltages be-
ing low. For proper operation, logic low input voltages
should be no higher than 0.4V with respect to the ground
pin voltage of the LTC4303. SDAIN and SDAOUT enter
a logic high state only when all devices on both SDAIN
and SDAOUT release high. The same is true for SCLIN
and SCLOUT. This important feature ensures that clock
stretching, clock synchronization, arbitration and the ac-
knowledge protocol always work, regardless of how the
devices in the system are tied to the LTC4303.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
OPERATIO
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms, as
described here.
Input to Output Offset Voltage
When a logic low voltage, V
LOW1
, is driven on any of the
LTC4303s data or clock pins, the LTC4303 regulates the
voltage on the opposite side of the part (call it V
LOW2
)
to a slightly higher voltage, as directed by the following
equation:
V
LOW2
= V
LOW1
+ 75mV + (V
CC
/R) " 20?(typical)
where R is the bus pull-up resistance in ohms. For ex-
ample, if a device is forcing SDAOUT to 10mV where
V
CC
= 3.3V and the pull-up resistor R on SDAIN is 10k,
then the voltage on SDAIN = 10mV + 75mV + (3.3/10000)
" 20 = 91.6mV (typical). See the Typical Performance
Characteristics section for curves showing the offset
voltage as a function of V
CC
and R.
Bus Stuck Low Time-Out
When SDAOUT or SCLOUT is low, an internal timer starts.
The timer is only reset when SDAOUT and SCLOUT are
both high. If they do not go high within 30ms (typical),
the connection between SDAIN and SDAOUT, and SCLIN
and SCLOUT is broken. After a delay of at least 40祍 the
LTC4303 automatically generates up to 16 clock pulses at
8.5kHz (typical) on SCLOUT in an attempt to unstick the
bus. When SDAOUT and SCLOUT go high, reconnection
occurs when the conditions described in the Start-Up
section above are satis ed.
When powering up into a bus stuck low condition, the
connection circuitry joining the SDA and SCL busses on
the I/O card with those on the backplane is not activated.
30ms after UVLO, automatic clocking takes place as
described above.
Propagation Delays
During a rising edge, the rise-time on each side is de-
termined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise-time occurs which is directly
proportional to the difference in capacitance between
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