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参数资料
| 型号： | LTC4303IMS8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 3/12页 |
| 文件大小： | 549K |
| 描述： | IC BUS BUFFER I2C 8-MSOP |
| 产品培训模块： | LTC4310 - Hot-Swappable I²C Isolators |
| 标准包装： | 50 |
| 类型： | 热交换开关 |
| 应用： | 通用型缓冲器/总线扩展器 |
| 内部开关： | 是 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
LTC4303
3
4303fb
ELECTRICAL CHARACTERISTICS
The ?/SPAN> denotes the speci cations which apply over the full operating
temperature range, otherwise speci cations are at T
A
= 25癈. V
CC
= 2.7V to 5.5V, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise speci ed.
Note 3: Pulsed less than 5?/SPAN>s.
Note 4: The connection circuitry always regulates the output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and V
CC
voltage is shown in the Typical Performance
Characteristics section.
Note 5: I
PULLUPAC
varies with temperature and V
CC
voltage, as shown in
the Typical Performance Characteristics section.
Note 6: Guaranteed by design, not tested in production.
Note 7: I
CC
test performed with connection circuitry active.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
HYS
SDA, SCL, Logic Input Threshold Voltage (Note 6)
50
mV
Hysteresis
t
PHL_ENABLE
Delay ENABLE High-Low to Disconnect V
CC
= 3.3V
300
ns
t
PHL_READY
Delay READY High-Low after Disconnect
10
ns
t
PLH_ENABLE
Delay ENABLE Low-High to Connect
V
CC
= 3.3V
?SPAN class="pst LTC4303CDD-TRPBF_2330545_8">
60
95
175
祍
t
PLH_READY
Delay READY Low-High after Connect
10
ns
I
OFF_READY
Ready Off Leakage Current
?SPAN class="pst LTC4303CDD-TRPBF_2330545_8">
?0
礎
Rise-Time Accelerators
I
PULLUPAC
Transient Boosted Pull-Up Current
Positive Transition on SDA, SCL, V
CC
= 2.7V,
2
3.5
5.5
mA
Slew Rate = 0.8V/祍 (Note 5)
Bus Stuck Low Timeout
t
TIMEOUT
Bus Stuck Low Timer
SDAOUT, SCLOUT = 0V
?
25
30
35
ms
Input-Output Connection
V
OS
Input-Output Offset Voltage
10k to V
CC
on SDA, SCL,
?
40
80
120
mV
2.7k to V
CC
on SDA, SCL
?SPAN class="pst LTC4303CDD-TRPBF_2330545_8">
50
100
150
mV
V
CC
= 3.3V, V
SDA/SCL
= 0.2V (Note 4)
C
IN
Digital Input Capacitance
(Note 6)
10
pF
SDAIN, SDAOUT, SCLIN, SCLOUT
V
IL, MAX
Input Logic Low Voltage
?SPAN class="pst LTC4303CDD-TRPBF_2330545_8">
0.4
V
I
LEAK
Input Leakage Current
SDA, SCL, V
CC
= 5.5V
?SPAN class="pst LTC4303CDD-TRPBF_2330545_8">
?
礎
V
OL
Output Low Voltage, Input = 0
SDA, SCL Pins, I
SINK
= 4mA, V
CC
= 2.7V
?SPAN class="pst LTC4303CDD-TRPBF_2330545_8">
0
0.19
0.3
V
Timing Characteristics
f
I2C, MAX
I
2
C Maximum Operating Frequency
(Note 6)
400
600
kHz
t
BUF
Bus Free Time Between Stop and Start (Note 6)
1.3
祍
Condition
t
HD, STA
Hold Time After (Repeated)
(Note 6)
100
ns
Start Condition
t
SU, STA
Repeated Start Condition Set-Up Time
(Note 6)
0
ns
t
SU, STO
Stop Condition Set-Up Time
(Note 6)
0
ns
t
HD, DATI
Data Hold Time Input
(Note 6)
0
ns
t
SU, DAT
Data Set-Up Time
(Note 6)
100
ns
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