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参数资料
| 型号： | LTC4306IUFD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | IC MUX 4CH 2-WIRE BUS 24-QFN |
| 产品培训模块： | LTC4310 - Hot-Swappable I²C Isolators |
| 标准包装： | 2,500 |
| 应用： | 带放大器的多路复用器 |
| 接口： | SMBus（2 线/I²C） |
| 电源电压： | 2.2 V ~ 5.5 V |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（5x4） |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
LTC4306
4306f
12
In all other cases, the LTC4306 communicates with the
master to resolve the fault. After the master broadcasts the
Alert Response Address (ARA), the LTC4306 will respond
with its address on the SDAIN line and release the ALERT
pin. The ALERT line will also be released if the LTC4306 is
addressed by the master.
The ALERT signal will not be pulled low again until a
different type of fault has occurred or the original fault is
cleared and it occurs again. Figure 2 shows the details of
how the ALERT pin is set and reset. The downstream bus
connection fault and faults that occur on unconnected
downstream buses are grouped together and generate a
single signal to drive ALERT. The stuck low timeout fault
has its own dedicated pathway to ALERT; however, once
a stuck low occurs, another one will not occur until the first
one is cleared. For these reasons, once the master has
established the LTC4306 as the source of the fault, it
should read register 0 to determine the specific problem,
take action to solve the problem, and clear the fault
promptly. All faults are cleared by writing a dummy data
byte to register 0, which is a read-only register.
For example, assume that a fault occurs, the master sends
out the ARA, and the LTC4306 successfully writes
its address onto SDAIN and releases its ALERT pin. The
master reads register 0 and learns that the ALERT2 logic
state bit is low. The master now knows that a device on
downstream bus 2 has a fault and writes to register 3 to
connect to bus 2, so that it can communicate with the
source of the fault. At this point, the master writes to
register 0 to clear the LTC4306 fault register.
I2C Device Addressing
Twenty-seven distinct bus addresses are configurable
using the three state ADR0, ADR1 and ADR2 pins. Table 1
shows the correspondence between pin states and ad-
dresses. Note that address bits a6 and a5 are internally
configured to 1 and 0 respectively. In addition, the LTC4306
responds to two special addresses. Address (1011 101) is
a mass write used to write all LTC4306’s, regardless of
their individual address settings. The mass write can be
masked by setting the Mass Write Enable bit of register 2
to zero. Address (0001 100) is the SMBus Alert Response
Address. Figure 3 shows data transfer over a 2-wire bus.
Supported Commands
Users must write to the LTC4306 using the SMBus Write
Byte protocol and read from it using the Read Byte
protocol. During fault resolution, the LTC4306 also
supports the Alert Response Address protocol. The
formats for these protocols are shown in Figure 4. Users
must follow the Write Byte protocol exactly to write to the
LTC4306; if a Repeated Start Condition is issued before a
Stop Condition, the LTC4306 ignores the attempted write,
and its control bits remain in their preexisting state. When
OPERATIO
U
D
4306 F02
VCC
Q
WRITE
REGISTER 0
RD
D
FAULT ON CONNECTED
DOWNSTREAM BUS
VCC
Q
WRITE
REGISTER 0
FAULT ON DISCONNECTED
DOWNSTREAM BUS
CONNECTION FAULT
ADDRESS LTC4306
STUCK BUS
LTC4306 RESPONDS
TO ARA
RD
ALERT
Figure 2. Setting and Resetting the ALERT Pin
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