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参数资料
| 型号： | LTC4312IMS#TRPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封装： | LEAD FREE, PLASTIC, MSOP-16 |
| 文件页数： | 15/20页 |
| 文件大小： | 190K |
| 代理商： | LTC4312IMS#TRPBF |
LTC4312
4
4312f
ELECTRICAL CHARACTERISTICS The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. VCC = VCC2 = 3.3V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ILEAK
Input Leakage Current
DISCEN = ENABLE1-2 = 5.5V
l
0.1
±10
μA
IACC(IN, HL)
ACC High, Low Input Current
VCC = 5V, VACC = 5V, 0V
l
±23
±40
μA
IACC(IN, Z)
Allowable Leakage Current in
Open State
VCC = 5V
l
±5
μA
IACC(EN, Z)
ACC High Z Input Current
VCC = 5V
l
±5
μA
VACC(L, TH)
ACC Input Low Threshold
Voltages
VCC = 5V
l
0.2VCC
0.3VCC
0.4VCC
V
VACC(H,TH)
ACC Input High Threshold
Voltages
VCC = 5V
l
0.7VCC
0.8VCC
0.9VCC
V
Stuck Low Timeout Circuitry
tTIMEOUT
Bus Stuck Low Timer
SDAOUT or SCLOUT < 0.3VCC
l
35
45
55
ms
VFAULT(OL)
FAULT Output Low Voltage
IFAULT = 3mA
l
0.4
V
IFAULT(OH)
FAULT Leakage Current
l
0.1
±5
μA
I2C Interface Timing
fSCL(MAX)
I2C Frequency Max
(Note 6)
l
400
kHz
tPDHL
SDA, SCL Fall Delay
VCC = 3V to 5.5V, CBUS = 50pF, IBUS = 1mA (Note 6)
60
100
ns
tf
SDA, SCL Fall Times
VCC = 3V to 5.5V, CBUS = 50pF, IBUS = 1mA (Note 6)
10
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive and all voltages are referenced to
GND unless otherwise indicated.
Note 3: SDAIN, SCLIN pulled low.
Note 4: VMIN = minimum of VCC and VCC2 if VCC2 > 2.25V else VMIN = VCC.
Note 5: VIL is tested for the following (VCC, VCC2) combinations:
(2.9V, 5.5V), (5.5V, 2.25V), (3.3V, 3.3V) and (5V, 0V).
Note 6: Guaranteed by design and not tested.
Note 7: Measured in a special DC mode with VSDA,SCL = VRTA(TH) + 1V.
The transient IRTA seen during rising edges when ACC is low will depend
on the bus loading condition and the slew rate of the bus. The LTC4312’s
internal slew rate control circuitry limits the maximum bus rise rate to
75V/μs by controlling the transient IRTA.
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