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参数资料
| 型号： | LTC4366HTS8-1#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 14/24页 |
| 文件大小： | 0K |
| 描述： | IC SURGE STOPPER HV TSOT-23-8 |
| 标准包装： | 2,500 |
| 电压 - 工作： | 9V |
| 电压 - 箝位： | 可调式 |
| 技术： | 混合技术 |
| 电路数： | 1 |
| 应用： | 自动 |
| 封装/外壳： | SOT-23-8 薄型，TSOT-23-8 |
| 供应商设备封装： | TSOT-23-8 |
| 包装： | 带卷 (TR) |
LTC4366-1/LTC4366-2
APPLICATIONS INFORMATION
V DD
M1
R SS(MAX) =
V IN(MIN) – 4.75V – 0.58V – V TH – ( 45μA ? R SS )
R IN(MAX) =
theV DD pin,andfinallythecurrentfromtheV SS pin(see
Figure 5.).
V IN(MIN) = (I VDD ? R IN ) + V D + V TH + V C1 + (I VSS ? R SS )
Using the Electrical Characteristics table for above
parameters:
V C1 = V UVLO2 = 4.75V (UVLO2 threshold)
I VDD = I VDD(STHI) = 9μA (I VDD start-up, gate high)
I VSS = I VSS(AMP) = 45μA (I VSS w/regulation amp)
V D = 0.58V
V IN(MIN) = (9μA ? R IN ) + 0.58V + V TH + 4.75V + (45μA???R SS )
When the MOSFET gate is fully enhanced, the OUT pin
voltage is equal to the supply voltage. This places another
constraint on the minimum supply voltage because the
charge pump increases the V SS current to 160μA. The C1
voltage is assumed to be clamped at 5.7V. These values
are specified as V Z(OUT) and I VSS(CP) (charge pump on)
in the table of Electrical Characteristics:
V IN(MIN) = V Z(OUT) + (I VSS(CP) ? R SS )
or
V IN(MIN) = 5.7V + (160μA ? R SS )
V IN
I RIN R IN
7.5μA D1
GATE
C G
The last V IN(MIN) equation sets the maximum value for
R SS . After choosing R SS the maximum value for R IN (for
that particular R SS ) is calculated from the first V IN(MIN)
equation:
V IN(MIN) – 5.7V
160μA
9μA
These two equations maximize the values of R SS and
R IN (reducing power dissipation) while still providing
the necessary V C1 voltage to turn the charge pump on.
Increasing the supply voltage beyond the minimum sup-
ply voltage increases the current and power in R SS while
reducing the time required to charge C1. Conditions that
may require an even smaller R SS(MAX) will be discussed
in the Maximum Supply Start-Up section.
Maximum Supply Start-Up
The maximum overvoltage supply may also exist during
start-up. The overvoltage protection circuitry has to wake
up before high voltage is passed to the load. Dynamically
the GATE is ramping up while C1 is charging. Capacitor
C1 must charge to the 2.55V UVLO1 threshold to turn on
the regulation amplifier and reference before the OUT pin
voltage exceeds the overvoltage regulation point, V REG .
These conditions may reduce the value of R SS below the
maximum value dictated by the minimum supply start-up
discussed above.
5.7V CIRCUITS
Z1
12V
I SHUNT1
LOGIC
TIMER
9μA
Z3
I SHUNT2 I BIAS
OUT
C1
V SS
+
–
V OUT
V C1
I C1
R LOAD
When current in R SS exceeds the current sourced from
the V SS pin (essentially I RIN ), the capacitor C1 begins to
charge. The voltage at the V SS pin when I RIN = I RSS is now
labeled V SS(MATCH) . The V SS pin voltage is the center of a
voltage divider between R IN and R SS after the Zener clamp
voltage from V DD to V SS is subtracted from the supply.
R SS
I RSS
436612 F05
V SS(MATCH) =
R SS
R SS + R IN
? ( V IN(MAX) – V Z(VDD) )
Figure 5. Simplified Block Diagram
As V IN increases the V SS(MATCH) voltage increases. If the
match voltage exceeds the overvoltage regulation point
(V REG ), then load is unprotected. This is true because
C1 will still need to charge to 2.55V while V SS already
14
For more information www.linear.com/LTC4366
436612fd
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