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参数资料
| 型号： | LTC4425EDD#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO12 |
| 封装： | 3 X 3 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, DFN-12 |
| 文件页数： | 18/20页 |
| 文件大小： | 239K |
| 代理商： | LTC4425EDD#PBF |
LTC4425
7
4425f
PIN FUNCTIONS
VOUT (Pin 1, 2): Output Pin of the Charger. Typically con-
nects to the top of the 2-cell supercap stack.
PROG (Pin 3): Charge Current Program and Charge
Current Monitor Pin. A resistor connected from PROG to
ground programs the charge current. In LDO mode, this
pin always servos to 1V. However, if the charge current
prole is turned on, this pin servos to a voltage between
1V and 0.1V depending on the input-to-output differential.
In all cases, the voltage on this pin always represents the
actual charge current.
SEL (Pin 4): Logic Input to Select One of the Two Possible
Clamp Voltages (VCLAMP). If the pin is a logic low, the
maximum voltage across any supercap of the stack is
2.45V. If the pin is a logic high, it is 2.7V. Do not oat
this pin.
FB (Pin 5): In LDO mode, output voltage is programmed
by a resistor divider from VOUT via the FB pin. In this
mode, the voltage on this pin always servos to the internal
reference voltage of 1.2V. If the FB pin is pulled up to VIN,
the LDO mode is disabled and the charge current prole
mode is turned on. Shorting the FB pin to GND turns off
charge current prole mode. Do not oat this pin.
EN (Pin 6): Digital Input to Enable the Charger. If this pin
is a logic high, the part is enabled and it draws only 20μA
of quiescent current from the input or output when idle.
If this pin is a logic low, the part is in shutdown mode and
draws less than 3μA. Do not oat this pin.
PFI_RET (Pin 7): This pin connects to the bottom of the
external resistor divider for the input power-fail compara-
tor. In shutdown mode, an internal switch opens up this
path to reduce the current drawn by the resistor divider.
PFO (Pin 8): Open Drain Output of the Power-Fail Com-
parator. This pin is driven to logic low if at least one of the
following conditions is true: (1) VIN is less than a value
programmed by an external divider via PFI, (2) VOUT has
not reached within 7.5% of its nal programmed value
in LDO mode, or (3) VOUT is not within 250mV of VIN in
charge current prole mode. When all these conditions
are false for at least 200ms, this pin goes high impedance
indicating that power is good.
PFI (Pin 9): Input to the Power-Fail Comparator. The input
voltage below which PFO pin indicates a power-fail condi-
tion can be programmed by connecting this pin to an
external resistor divider between VIN and PFI_RET pin.
VMID (Pin 10): Connects to the Midpoint of the 2-Cell
supercap stack. An internal leakage balancing amplier
drives this pin to a voltage which is exactly half of VOUT.
VIN (Pin 11, 12): Input Power Pin. Typically connected to
a DC source like a Li-Ion/Polymer battery or a USB port.
This pin should be bypassed with a low-ESR ceramic
capacitor.
GND (Exposed Pad Pin 13): GND. The Exposed Pad should
be connected to a continuous ground plane on the second
layer of the printed circuit board by several vias directly
under the part to achieve optimum thermal conduction.
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