参数资料
型号: LTC6404IUD-4#PBF
厂商: Linear Technology
文件页数: 19/28页
文件大小: 0K
描述: IC AMP/DRIVER DIFF 16-QFN
标准包装: 121
类型: ADC 驱动器
应用: 数据采集
安装类型: 表面贴装
封装/外壳: 16-WFQFN 裸露焊盘
供应商设备封装: 16-QFN-EP(3x3)
包装: 管件
产品目录页面: 1323 (CN2011-ZH PDF)
LTC6404
26
6404f
APPLICATIONS INFORMATION
Figure 11. Interfacing the LTC6404-1 to a High Speed 105Msps ADC
other external sources of noise from being converted to
differential noise due to divider mismatches in the feedback
networks. It is also recommended that the resistive feed-
back networks be comprised of 1% resistors (or better)
to enhance the output common mode rejection. This will
also prevent VOCM referred common mode noise of the
common mode amplier path (which cannot be ltered)
from being converted to differential noise, degrading the
differential noise performance.
Feedback factor mismatch has a weak effect on distortion.
Using 1% or better resistors should prevent mismatch
from impacting amplier linearity. However, in single
supply level shifting applications where there is a voltage
difference between the input common mode voltage and
the output common mode voltage, resistor mismatch can
make the apparent voltage offset of the amplier appear
worse than specied.
In general, the apparent input referred offset induced by
feedback factor mismatch is given by the equation:
VOSDIFF(APPARENT) ≈ (VINCM – VOCM) Δβ
where
Δβ =
++
R
RR
R
RR
I
IF
I
IF
2
22
1
11
Interfacing the LTC6404 to A/D Converters
The LTC6404’s rail-to-rail output and fast settling time make
the LTC6404 ideal for interfacing to low voltage, single
supply, differential input ADCs. The sampling process of
ADCs create a sampling glitch caused by switching in the
sampling capacitor on the ADC front end which momentarily
“shorts” the output of the amplier as charge is transferred
between the amplier and the sampling cap. The amplier
must recover and settle from this load transient before
this acquisition period ends for a valid representation of
the input signal. In general, the LTC6404 will settle much
more quickly from these periodic load impulses than
from a 2V input step, but it is a good idea to either use
the ltered outputs to drive the ADC (Figure 11 shows an
example of this), or to place a discrete R-C lter network
between the differential unltered outputs of the LTC6404
and the input of the ADC to help absorb the charge transfer
required during the ADC sampling process. The capaci-
tance of the lter network serves as a charge reservoir
to provide high frequency charging during the sampling
process, while the two resistors of the lter network are
used to dampen and attenuate any charge kickback from
the ADC. The selection of the R-C time constant is trial
and error for a given ADC, but the following guidelines
are recommended: Choosing too large of a resistor in the
decoupling network (leaving insufcient settling time)
+
1
SHDN
5
6
IN
7
OUT+
8
OUTF+
16
15
IN+
NC
14
OUT
13
OUTF
AIN+
AIN
100Ω
2
V+
3
V
V+
V
3.3V
VOCM
12
V
11
V+
10
V+
9
V
6404 F11
LTC6404-1
LTC2207
VIN
2VP-P
SHDN
100Ω
0.1μF
3.3V
4
0.1μF
CONTROL
GND
VDD
D15
D0
0.1μF
VCM
2.2μF
3.3V
1μF
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