参数资料
型号: LTC6406IMS8E#PBF
厂商: Linear Technology
文件页数: 8/24页
文件大小: 0K
描述: IC AMP/DRIVER DIFF 8-MSOP
标准包装: 50
类型: ADC 驱动器
应用: 数据采集
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)裸露焊盘
供应商设备封装: 8-MSOP-EP
包装: 管件
LTC6406
16
6406fc
+
RF
V–OUT
V+OUT
VVOCM
VOCM
6406 F05
RF
RI
+
VINP
+
VCM
+
VINM
V–IN
V+IN
APPLICATIONS INFORMATION
Input Common Mode Voltage Range
The LTC6406’s input common mode voltage (VICM) is
dened as the average of the two input voltages, V+IN, and
V–IN. At the inputs to the actual op amp, the range extends
from Vto V+. This makes it easy to interface to a wide
range of common mode signals, from ground referenced to
VCC referenced signals. Moreover, due to external resistive
divideractionofthegainandfeedbackresistors,theeffective
range of signals that can be processed is even wider. The
input common mode range at the op amp inputs depends
on the circuit conguration (gain), VOCM and VCM (refer to
Figure 5). For fully differential input applications, where
VINP = –VINM, the common mode input is approximately:
V
ICM =
V+IN + V–IN
2
≈ V
OCM
R
I
R
I + RF
+
V
CM
R
F
R
F + RI
With single-ended inputs, there is an input signal compo-
nent to the input common mode voltage. Applying only
VINP (setting VINM to zero), the input common voltage is
approximately:
V
ICM =
V+IN + V–IN
2
≈ V
OCM
R
I
R
I + RF
+
V
CM
R
F
R
F + RI
+
V
INP
2
R
F
R
F + RI
Use the equations above to check that the VICM at the op
amp inputs is within range (Vto V+).
Figure 5. Circuit for Common Mode Range
Manipulating the Rail-to-Rail Input Stage with VTIP
To achieve rail-to-rail input operation, the LTC6406 features
an NPN input stage in parallel with a PNP input stage. When
the input common mode voltage is near V+, the NPNs are
active while the PNPs are off. When the input common
mode is near V, the PNPs are active while the NPNs are
off. At some range in the middle, both input stages are
active. This ‘hand-off’ operation happens automatically.
In the QFN package, a special pin, VTIP, is made available
that can be used to manipulate the ‘hand-off’ operation
between the NPN and PNP input stages. By default, the
VTIP pin is internally biased by an internal resistive divider
between the supplies, developing a default 1.55V voltage
with a 3V supply. If desired, VTIP can be overdriven by an
external voltage (the Thevenin equivalent resistance is
approximately 15k).
If VTIP is pulled closer to V, the range over which the NPN
input pair remains active is increased, while the range over
which the PNP input pair is active is reduced. In applica-
tions where the input common mode does not come close
to V, this mode can be used to further improve linearity
beyond the specied performance.
If VTIP is pulled closer to V+, the range over which the PNP
input pair remains active is increased, while the range over
which the NPN input pair is active is reduced. In applica-
tions where the input common mode does not come close
to V+, this mode can be used to further improve linearity
beyond the specied performance.
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