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参数资料
| 型号： | LTC6801IG#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO36 |
| 封装： | LEAD FREE, PLASTIC, SSOP-36 |
| 文件页数： | 10/28页 |
| 文件大小： | 265K |
| 代理商： | LTC6801IG#PBF |
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LTC6801
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Self Test Pins
The SLT pin is used to initiate a self test. It is congured
as an open collector input/output. The pin should be nor-
mally tied to VREG with a resistor greater than or equal to
100k or oated. The pin may be pulled low at any time to
initiate a self test cycle.
The device will automatically initiate a self test if SLT has
not been externally activated for 1024 measurement cycles,
and pull down the SLT pin internally to indicate that it is
in self test mode.
The SLTOK pin is a simple logic output. If the previous self
test failed the output is held low, otherwise the output will
be high. The SLTOK pin is high upon power-up. The SLTOK
output can be connected to a microcontroller through an
isolation path.
The LTC6801 status output will remain active while the
SLTOK pin is low. The LTC6801 will continue to monitor
cells if the self test fails. If the next self test passes, the
SLTOK output returns high.
Reference and Comparator Verication
A secondary internal bandgap voltage reference (REF2)
is included in the LTC6801 to aid in verication of the
reference and comparator. During the self test cycle, the
comparator and main reference are used to measure the
REF2 voltage.
To verify the comparator functionality, the upper and
lower thresholds are rst set in a close window around
the expected REF2 voltage and the comparator output is
veried. Then the upper threshold is set below the REF2
voltage and the comparator output is veried again. Lastly,
the lower threshold is set above the REF2 voltage and the
comparator output is veried a third time.
The self test guarantees that VREF is within 5% of the
specied nominal value. Also, this test guarantees the
analog portion of the ADC is working.
High Voltage Multiplexer Verication
The most dangerous failure mode of the high voltage
multiplexer would be a stuck bit condition in the address
decoder. Such a fault would cause some channels to be
measured repeatedly while other channels are skipped.
A skipped channel could mean a bad cell reading is not
detectable. Other multiplexer failures, like the simultaneous
selection of multiple channels, or shorts in the signal path,
would result in an undervoltage or overvoltage condition
on at least one of the channels.
The LTC6801 incorporates circuitry to ensure that
all requested channels are measured during each
measurement cycle and none are skipped. If a channel is
skipped, an error is agged during the self test cycle.
ADC Decimation Filter Verication
The ADC decimation lter test veries that the digital cir-
cuits in the ADC are working, i.e. there are no stuck bits
in the ADC output register. During each self test cycle,
the LTC6801 feeds two test waveforms into the ADC. The
internally generated waveforms were designed to generate
complementary zebra patterns (alternating 0’s and 1’s) at
the ADC output. If either of the waveforms generates an
incorrect output value, an error is agged during the self
test cycle.
Open Cell Connection Detection
The open connection detection algorithm ensures that an
open circuit is not misinterpreted as a valid cell reading.
APPLICATIONS INFORMATION
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相关代理商/技术参数 |
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| LTC6801IGTRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:Independent Multicell Battery Stack Fault Monitor |
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| LTC6802-1_1 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Multicell Battery Stack Monitor |
| LTC6802-2 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Multicell Battery Stack Monitor |
| LTC6802IG-1 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Multicell Battery Stack Monitor |
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