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| 型号： | LTC6905CS5-80#TRMPBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC OSC SILICON 80MHZ TSOT23-5 |
| 产品目录绘图： | TSOT23-5 Series Top |
| 标准包装： | 1 |
| 类型： | 振荡器 - 硅 |
| 频率： | 80MHz |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电流 - 电源： | 7mA |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | SOT-23-5 细型，TSOT-23-5 |
| 包装： | 标准包装 |
| 供应商设备封装： | TSOT-23-5 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 1715 (CN2011-ZH PDF) |
| 其它名称： | LTC6905CS5-80#TRMPBFDKR |
LTC6905-XXX Series
6
6905xfa
APPLICATIO S I FOR ATIO
WU
UU
START-UP TIME
The start-up and settling time to within 1% of the final
frequency is typically 100
s.
MAXIMUM OUTPUT LOAD
The LTC6905 output (Pin 5) can drive a capacitive load
(CLOAD) of 5pF or more. Performance driving a CLOAD
greater than 5pF depends on the oscillator’s frequency
(fOSC) and output resistance (ROUT). The output rise time
or fall time due to ROUT and CLOAD is equal to 2.2 ROUT
CLOAD(from 10% to 90% of the rise or fall transition). If the
total output rise time plus fall time is arbitrarily specified
to be equal to or less than 20% of the oscillator’s period (1/
fOSC), then the maximum output CLOAD in picofarads (pF)
should be equal to or less than [45454/(ROUT fOSC)]
(ROUT in ohms and fOSC in MHz).
Example: An LTC6905-100 is operating with a 3V power
supply and is set for a fOSC = 50MHz.
ROUT with V+ = 3V is 27 (using the ROUT vs V+ graph in
the Typical Performance Characteristics).
The maximum output CLOAD should be equal to or less
than [45454/(27 50)] = 33.6pF.
The lowest resistive load Pin 5 can drive can be calculated
using the minimum high level output voltage in the Elec-
trical Characteristics. With a V+ equal to 5.5V and 4mA
output current, the minimum high level output voltage is
5.2V and the lowest resistive load Pin 5 can drive is 1.30k
(5.2V/4mA). With a V+ equal to 2.7V and 4mA output
current, the minimum high level output voltage is 2.4V and
the lowest resistive load Pin 5 can drive is 600
(2.4V/4mA).
FREQUENCY ACCURACY AND POWER SUPPLY NOISE
The frequency accuracy of the LTC6905 may be affected
when its power supply generates noise with frequency
contents equal to fMO/64 or its multiples. fMO is the
highest frequency for an LTC6905-XXX which is with
DIV = V+ (
÷1). This is also the frequency indicated in the
part number (i.e., LTC6905-100, fMO = 100MHz). fMO/64
is the master oscillator control loop frequency. For ex-
ample, if the LTC6905-80 with a master oscillator fre-
quency of 80MHz is powered by a switching regulator,
then the oscillator frequency may show an additional
error if the switching frequency is 1.4MHz (80MHz/64).
The magnitude of this effect is heavily dependent on
supply bypass and routing.
JITTER AND POWER SUPPLY NOISE
If the LTC6905 is powered by a supply that has frequency
content equal to the output frequency then the output jitter
may increase. In addition, power supply ripple in excess of
20mV at any frequency may increase jitter.
Higher divide ratios will result in lower percentage jitter.
For example, jitter percentage of the LTC6905-80 operat-
ing at 20MHz is lower than for the same part operating at
80MHz. Please consult the Jitter vs Frequency graph
showing jitter at various divider ratios.
LTC6905 SUGGESTED CRITICAL COMPONENT
LAYOUT
In order to provide the specified performance, it is re-
quired that the supply bypass capacitor be placed as close
as possible to the LTC6905. The following additional rules
should be followed for best performance:
1) The bypass capacitor must be placed as close as
possible to the LTC6905, and no vias should be placed
between the capacitor and the LTC6905. The bypass
capacitor must be on the same side of the circuit board
as the LTC6905.
2) If a ground plane is used, the connection of the LTC6905
to the ground plane should be as close as possible to the
LTC6905 GND pin and should be composed of multiple,
high current capacity vias.
Figure 2. LTC6905 Suggested Critical Component Layout
LTC6905
6905x F02
C
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