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参数资料
| 型号： | LTC6915IDE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 2/18页 |
| 文件大小： | 0K |
| 描述： | IC PGA DIGITAL PREC 0DRFT 12DFN |
| 标准包装： | 91 |
| 放大器类型： | 仪表 |
| 电路数： | 1 |
| 输出类型： | 满摆幅 |
| 转换速率： | 0.2 V/µs |
| 增益带宽积： | 200kHz |
| 电流 - 输入偏压： | 4nA |
| 电压 - 输入偏移： | 5µV |
| 电流 - 电源： | 1.73mA |
| 电压 - 电源，单路/双路(±)： | 2.7 V ~ 11 V，±1.35 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-WFDFN 裸露焊盘 |
| 供应商设备封装： | 12-DFN-EP（4x3） |
| 包装： | 管件 |
LTC6915
10
6915fb
pin FuncTions
IN– (Pin 1/Pin 2): Inverting Analog Input.
SHDN (Pin 1 GN Package Only): Shutdown Pin. The IC is
shut down when SHDN is tied to V+. An internal current
source pulls this pin to V– when floating.
IN+ (Pin 2/Pin 3): Noninverting Analog Input.
V– (Pin 3/Pin 4): Negative Supply.
CS(D0) (Pin 4/Pin 6): TTL Level Input. When in serial
control mode, this pin is the chip select input (active low);
in parallel control mode, this pin is the LSB of the parallel
gain control code.
DIN(D1) (Pin 5/Pin 7): TTL Level Input. When in serial
control mode, this pin is the serial input data; in paral-
lel mode, this pin is the second LSB of the parallel gain
control code.
HOLD_THRU (Pin 5 GN Package Only): TTL Level Input
for Parallel Control Mode. When HOLD_THRU is high, the
parallel data is latched in an internal D-latch.
CLK(D2) (Pin 6/Pin 8): TTL Level Input. When in serial
control mode, this pin is the clock of the serial interface;
in parallel mode, this pin is the third LSB of the parallel
gain control code.
DOUT(D3) (Pin 7/Pin 9): TTL Level Input. When in serial
control mode, this pin is the output of the serial data; in
parallel mode, this pin is the MSB of the 4-bit parallel
gain control code. In parallel mode operation, if the data
in to DOUT (Pin 9) is from a voltage source greater than V+
(Pin12),thenconnectaresistorbetweenthevoltagesource
and DOUT to limit the current into Pin 9 to 5mA or less.
DGND (Pin 8/Pin 10): Digital Ground.
PARALLEL_SERIAL (Pin 9/Pin 11): Interface Selection
Input. When tied to V+, the interface is in parallel mode,
i.e., the PGA gain is defined by the parallel codes (D3 ~
D0), i.e., CS(D0), DATA(D1), CLK(D2), and DOUT(D3).
When PARALLEL_SERIAL pin is tied to V–, the PGA gain
is set by the serial interface.
REF (Pin 10/Pin 13): Voltage Reference for PGA output.
OUT (Pin 11/Pin 15): Amplifier Output. The typical current
sourcing/sinking of the OUT pin is 1mA. For minimum
gain error, the load resistance should be 1k or greater
(refer to the Output Voltage Swing vs Output Current and
Gain Error vs Load Resistance in the Typical Performance
Characteristics section).
V+ (Pin 12/Pin 16): Positive Supply.
SENSE (Pin 14 GN Package Only): Sense Pin. When the
PGA drives a low resistance load and the interconnect
resistance between the OUT pin and the load is not neg-
ligible, tying the SENSE pin as close as possible to the
load can improve the gain accuracy.
(DFN/GN)
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| LTC6915IGN#PBF | 制造商:Linear Technology 功能描述:INSTR-AMPLIFIER 200KHZ 125DB 制造商:Linear Technology 功能描述:INSTR-AMPLIFIER 200KHZ 125DB SSOP-16 制造商:Linear Technology 功能描述:INSTR-AMPLIFIER, 200KHZ, 125DB, SSOP-16 |
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