参数资料
型号: LTC6943HGN#PBF
厂商: Linear Technology
文件页数: 5/16页
文件大小: 0K
描述: IC BUILDNG BLK SWCAP DUAL 16SSOP
标准包装: 100
应用: 切换电容构建块
输入电压: 5 V ~ 18 V
输出数: 1
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-SSOP
包装: 管件
LTC6943
TEST CIRCUITS
Test Circuit 1. Leakage Current Test
Test Circuit 2. R ON Test
(6, 11, 5, 16)
(7, 12, 4, 13)
(6, 11, 5, 16)
(7, 12, 4, 13)
NOTE: TO OPEN SWITCHES,
0V TO 10V
A
+
(9, 10, 1, 2)
S1 AND S3 PIN 14,
SHOULD BE CONNECTED
TO V –. TO OPEN S2, S4, THE
C OSC PIN 14 SHOULD BE
CONNECTED TO V+ C OSC
+
VIN
100 μ A to 1mA
A
(9, 10, 1, 2)
6943 ? TC01
CURRENT SOURCE
6943 ? TC02
Test Circuit 3. Oscillator Frequency, f OSC
Test Circuit 4. CMRR Test
6
7
V OUT
(TEST PIN) 1
V–
15
V+
+
3
LTC6943
C OSC
14
8
9
1 μ F
1 μ F
CAPACITORS ARE
NOT ELECTROLYTIC
4
10
+
IV
5
( )
6943 ? TC03
+
11
V – ≤ V CM ≤ V +
CMRR = 20 LOG
V CM
V OUT
12
NOTE: FOR OPTIMUM CMRR, THE C OSC SHOULD
BE LARGER THAN 0.0047 μ F, AND
THE SAMPLING CAPACITOR ACROSS
PINS 9 AND 10 SHOULD BE PLACED
APPLICATIO S I FOR ATIO
OVER A SHIELD TIED TO PIN 8
6943 ? TC04
Common Mode Rejection Ratio (CMRR)
1/2 LTC6943
The LTC6943, when used as a differential to single-ended
converter rejects common mode signals and preserves
differential voltages (Figure 1). Unlike other techniques,
6
C +
9
7
the LTC6943’s CMRR does not degrade with increasing
common mode voltage frequency. During the sampling
V D
+
C S
V D
+
C H
mode, the impedance of Pins 1, 2 (and 9, 10) should be
balanced, otherwise, common mode signals will appear
C – 10
differentially. The value of the CMRR depends on the value
of the sampling and holding capacitors (C S , C H ) and on the
sampling frequency. Since the common mode voltages
V CM
+
11
12
are not sampled, the common mode signal frequency can
well exceed the sampling frequency without experiencing
aliasing phenomena. The CMRR of Figure 1 is measured
by shorting Pins 6 and 11 and by observing, with a
C S , C H ARE MYLAR OR POLYPROPYLENE
6943 ? AI01
Figure 1. Differential to Single-Ended Converter
6943f
5
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