参数资料
型号: LTC6943HGN#TRPBF
厂商: Linear Technology
文件页数: 6/16页
文件大小: 0K
描述: IC BUILDNG BLK SWCAP DUAL 16SSOP
标准包装: 2,500
应用: 切换电容构建块
输入电压: 5 V ~ 18 V
输出数: 1
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-SSOP
包装: 带卷 (TR)
LTC6943
APPLICATIO S I FOR ATIO
precision DVM, the change of the voltage across C H with
respect to an input CM voltage variation. During the
sampling and holding mode, charges are being trans-
ferred and minute voltage transients will appear across the
holding capacitor. Although the R ON on the switches is low
enough to allow fast settling, as the sampling frequency
increases, the rate of charge transfer increases and the
average voltage measured with a DVM across it will
increase proportionally; this causes the CMRR of the
sampled data system, as seen by a “continuous” instru-
ment (DVM), to decrease (Figure 2).
Switch Charge Injection
Figure 3 shows one out of the eight switches of the
LTC6943, configured as a basic sample-and-hold circuit.
When the switch opens, a ‘‘hold step’’ is observed and its
magnitude depends on the value of the input voltage.
Figure 4 shows charge injected into the hold capacitor. For
instance, a 2pCb of charge injected into a 0.01 μ F capacitor
causes a 200 μ V hold step. As shown in Figure 4, there is
a predictable and repeatable charge injection cancellation
when the input voltage is close to half the supply voltage
of the LTC6943. This is a unique feature of this product,
containing charge-balanced switches fabricated with a
self-aligning gate CMOS process. Any switch of the
LTC6943, when powered with symmetrical dual supplies,
will sample-and-hold small signals around ground with-
out any significant error.
Shielding the Sampling Capacitor for Very High CMRR
Internal or external parasitic capacitors from the C + pin(s)
to ground affect the CMRR of the LTC6943 (Figure 1).
The common mode error due to the internal junction
capacitances of the C + Pin(s) 1 and 9 is cancelled through
internal circuitry. The C + pin, therefore, should be used as
the top plate of the sampling capacitor. A shield placed
underneath the sampling capacitor and connected to C –
helps to boost the CMRR to 120dB (Figure 5).
Excessive external parasitic capacitance between the C –
pins and ground indirectly degrades CMRR; this becomes
visible especially when the LTC6943 is used with clock
frequencies above 2kHz. Because of this, if a shield is
used, the parasitic capacitance between the shield and
circuit ground should be minimized.
It is recommended that the outer plate of the sampling
capacitor be connected to the C – pin(s).
C OSC Pin (14)
The C OSC pin can be used with an external capacitor, C OSC ,
connected from Pin 14 to Pin 15, to modify the internal
oscillator frequency. If Pin 16 is floating, the internal 24pF
capacitor, plus any external interpin capacitance, set the
oscillator frequency around 190kHz with ± 5V supply. The
typical performance characteristics curves provide the
necessary information to set the oscillator frequency for
various power supply ranges. Pin 14 can also be driven
with an external CMOS level clock to override the internal
140
120
C S = C H = 1 μ F
oscillator.
C S = 1 μ F, C H = 0.1 μ F
5V
100
1
5
+
80
1/8 LTC6943
1/2 LTC1013
V OUT
60
V IN
1000pF
–5V
40
V +
SAMPLE
20
100
1k
10k
100k
0V
HOLD TO PIN 14
6943 ? AI03
f OSC (Hz)
6943 ? AI02
Figure 2. CMRR vs Sampling Frequency
Figure 3
6943f
6
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