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参数资料
| 型号： | LTC6992CS6-4#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/34页 |
| 文件大小： | 0K |
| 描述： | IC OSC SILICON 1MHZ TSOT23-6 |
| 产品培训模块： | TimerBlox Family Timing Devices |
| 产品目录绘图： | LTC699_TSOT-23 |
| 特色产品： | TimerBlox? |
| 标准包装： | 2,500 |
| 系列： | TimerBlox® |
| 类型： | 振荡器 - 硅 |
| 频率： | 3.81Hz ~ 1MHz |
| 电源电压： | 2.25 V ~ 5.5 V |
| 电流 - 电源： | 365µA |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | SOT-23-6 细型，TSOT-23-6 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | TSOT-23-6 |
| 安装类型： | 表面贴装 |
| 配用： | DC1562A-C-ND - BOARD EVAL LTC6992-1 |
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LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
22
69921234fc
Power Supply Current
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under any
condition using the following equation:
If NDIV = 1 (DIVCODE = 0 or 15):
IS(TYP) ≈ V+ fOUT 39pF +CLOAD
(
)
+
V+
320k
+
V+ Duty Cycle
RLOAD
+ 2.2 ISET + 85A
If NDIV > 1 (DIVCODE = 1 or 14):
IS(TYP) ≈ V+ NDIV fOUT 27pF
+ V+ fOUT 28pF + CLOAD
(
)
+
V+
320k
+
V+ Duty Cycle
RLOAD
+ 2.6 ISET + 90A
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES
The LTC6992 is a 2.4% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Figure14showsexamplePCBlayoutsforboththeTSOT-23
and DFN packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6992. These layouts are
a guide and need not be followed exactly.
applicaTions inForMaTion
1. Connect the bypass capacitor, C1, directly to the V+ and
GND pins using a low inductance path. The connection
from C1 to the V+ pin is easily done directly on the top
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that,C1’sGNDconnectioncanbeaccomplishedthrough
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1μF ceramic capacitor.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place RSET as close as possible to the SET pin and
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
4. Connect RSET directly to the GND pin. Using a long path
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
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