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参数资料
| 型号： | LTC6993MPS6-4#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/26页 |
| 文件大小： | 0K |
| 描述： | IC MULTIVIBRATOR MONO TSOT23-6 |
| 特色产品： | TimerBlox? |
| 标准包装： | 2,500 |
| 系列： | LTC®6993 |
| 逻辑类型： | 单稳态 |
| 独立电路： | 1 |
| 施密特触发器输入： | 无 |
| 传输延迟： | 11ns |
| 输出电流高，低： | 16mA，16mA |
| 电源电压： | 2.25 V ~ 5.5 V |
| 工作温度： | -55°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 细型，TSOT-23-6 |
| 供应商设备封装： | TSOT-23-6 |
| 包装： | 带卷 (TR) |
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
18
69931234fb
ISET Extremes (Master Oscillator Frequency Extremes)
When operating with ISET outside of the recommended
1.25A to 20A range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
The oscillator will still function with reduced accuracy for
ISET < 1.25A. At approximately 500nA, the oscillator will
stop. Under this condition, the output pulse can still be
initiated, but will not terminate until ISET increases and
the master oscillator starts again.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Settling Time
Following a 2
× or 0.5× step change in ISET, the output
pulse width takes approximately six master clock cycles
(6 tMASTER) to settle to within 1% of the final value. An
exampleisshowninFigure10,usingthecircuitinFigure 8.
Coupling Error
The current sourced by the SET pin is used to bias the
internal master oscillator. The LTC6993 responds to
changesinISETalmostimmediately,whichprovidesexcel-
lent settling time. However, this fast response also makes
the SET pin sensitive to coupling from digital signals, such
as the TRIG input.
Even an excellent layout will allow some coupling between
TRIG and SET. Additional error is included in the speci-
fied accuracy for NDIV = 1 to account for this. Figure 11
shows that ÷1 supply variation is dependent on coupling
from rising or falling trigger inputs and, to a lesser extent,
output polarity.
A very poor layout can actually degrade performance
further. The PCB layout should avoid routing SET next to
TRIG (or any other fast-edge, wide-swing signal).
APPLICATIONS INFORMATION
Figure 10. Typical Settling Time
VCTRL
2V/DIV
TRIG
5V/DIV
OUT
5V/DIV
PULSE WIDTH
2s/DIV
LTC6993-1
V+ = 3.3V
DIVCODE = 0
RSET = 200k
RMOD = 464k
tOUT = 3s AND 6s
20s/DIV
69931234 F10
SUPPLY (V)
2
–1.0
DRIFT
(%)
–0.8
–0.4
–0.2
0
1.0
0.4
3
4
69931234 F11
–0.6
0.6
0.8
0.2
5
6
RSET = 50k
NDIV = 1
LTC6993-1
POL = 0
LTC6993-1
POL = 1
LTC6993-3
POL = 1
LTC6993-3
POL = 0
Figure 11. tOUT Drift vs Supply Voltage
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC6994-1 | 制造商:LINER 制造商全称:Linear Technology 功能描述:TimerBlox: Delay Block/ Debouncer |
| LTC6994-2 | 制造商:LINER 制造商全称:Linear Technology 功能描述:TimerBlox: Delay Block/ Debouncer |
| LTC6994CDCB-1#PBF | 制造商:Linear Technology 功能描述:DELAY BLOCK/DEBOUNCER 5.5V DFN-6 制造商:Linear Technology 功能描述:DELAY BLOCK/DEBOUNCER, 5.5V, DFN-6 制造商:Linear Technology 功能描述:SC-Timing, Cut Tape Delay with Rising or Falling Edge Trigger 制造商:Linear Technology 功能描述:DELAY BLOCK/DEBOUNCER, 5.5V, DFN-6, Operating Mode:Monostable, Supply Voltage Min:2.25V, Supply Voltage Max:5.5V, Digital IC Case Style:DFN, No. of Pins:6, Operating Temperature Min:0C, Operating Temperature Max:70C , RoHS Compliant: Yes |
| LTC6994CDCB-1#TRMPBF | 功能描述:IC DELAY LINE 6-DFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 延迟线 系列:TimerBlox® 标准包装:2,500 系列:- 标片/步级数:- 功能:多个，不可编程 延迟到第一抽头:10ns 接头增量:- 可用的总延迟:10ns 独立延迟数:4 电源电压:4.75 V ~ 5.25 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOIC 包装:带卷 (TR) |
| LTC6994CDCB-1#TRPBF | 功能描述:IC DELAY LINE 6-DFN RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 延迟线 系列:TimerBlox® 标准包装:2,500 系列:- 标片/步级数:- 功能:多个，不可编程 延迟到第一抽头:10ns 接头增量:- 可用的总延迟:10ns 独立延迟数:4 电源电压:4.75 V ~ 5.25 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SOIC 包装:带卷 (TR) |
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