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参数资料
| 型号： | LTC699IS8#TR |
| 厂商： | Linear Technology |
| 文件页数： | 3/4页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISORY CIRCUIT MPU 8SOIC |
| 标准包装： | 2,500 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 4.65V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
LTC699
PI FU CTIO S
V CC : +5V supply input. The V CC pin should be bypassed
with a 0.1 μ F capacitor.
GND: Ground pin.
RESET: Open drain output for μ P reset control. When V CC
falls below the reset voltage threshold (4.65V typically),
RESET goes active low. After V CC returns to 5V, the reset
pulse generator forces RESET to remain active low for a
minimum of 140ms . When the watchdog timer is enabled
but not serviced prior to the time-out period, the reset
pulse generator also forces RESET to active low for a mini-
mum of 140ms for every time-out period (see Figure 2).
WDI: Watchdog Input, WDI, is a three level input. Driving
WDI either high or low fo r longer than the watchdog time-
out period forces RESET low. Floating WDI disables the
Watchdog Timer. The timer resets itself with each transition
of the Watchdog Input (see Figure 2).
TYPICAL PERFOR A CE C HARA C TERISTICS
5
RESET Output Voltage vs
Supply Voltage
232
Reset Active Time vs
Temperature
4.66
Reset Voltage Threshold vs
Temperature
4
3
T A = 25°C
EXTERNAL PULLUP = 10 μ A
224
216
V CC = 5V
4.65
4.64
2
208
200
4.63
4.62
1
192
4.61
0
0
1
2
3
4
5
184
–50 –25
0
25
50
75
100 125
4.60
–50 –25
0
25
50
75
100
125
SUPPLY VOLTAGE (V)
LTC699 G01
A PPLICATI
S I FOR ATIO
Microprocessor Reset
TEMPERATURE ( ° C)
LTC699 G02
TEMPERATURE ( ° C)
LTC699 G03
The LTC699 uses a bandgap voltage reference and a
precision voltage comparator C1 to monitor the 5V supply
input V CC (see BLOCK DIAGRAM). When V CC falls below
the reset voltage threshold, the RESET output is forced to
active low state. The reset voltage threshold accounts for
a 5% variation on V CC , so the RESET output becomes
active low when V CC falls below 4.65V typical. On power-
up, the RESET signal is held active low for a minimum of
140ms after reset voltage threshold is reached to allow the
power supply and microprocessor to stabilize. On power-
down, the RESET signal remains active low even with V CC
as low as 1V. This capability helps hold the microproces-
sor in stable shutdown condition. Figure 1 shows the
timing diagram of the RESET signal.
The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at V CC pin do not
activate the RESET output. Response time is typically
10 μ s. To help prevent mistriggering due to transient loads,
V CC pin should be bypassed with a 0.1 μ F capacitor with the
leads trimmed as short as possible.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
3
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