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参数资料
| 型号： | LTI2911ITS8-3#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封装： | PLASTIC, MO-193, TSOT-23, 8 PIN |
| 文件页数： | 15/20页 |
| 文件大小： | 245K |
| 代理商： | LTI2911ITS8-3#TR |
LTC2911
4
2911f
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VADJ = 0.55V, VPFI = 0.55V, V1 = 3.3V unless otherwise noted. (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tP,PF
PFI Comparator Propagation Delay to PFO
VPFI Driven Beyond Threshold
VPFT by More Than 10%
l
8
30
80
s
tUV
V1, V2, ADJ Undervoltage Detect to RST Low
VX Less Than Threshold VRTX by
More Than 10%
l
8
30
80
s
VOH
RST, PFO Output Voltage High (Note 5)
IRST = –1A
l
V1 – 1
V1
V
VOL
RST, PFO Output Voltage Low (Note 6)
VCC = 0.5V, I = 5A
VCC = 1V, I = 100A
VCC = 3V, I = 2.5mA
l
0.01
0.10
0.15
0.30
V
tRST(EXT)
Reset Timeout Period, External
CTMR = 2.2nF
l
15
20
27
ms
tRST(INT)
Reset Timeout Period, Internal
VTMR = V1
l
140
200
280
ms
VTMR(INT)
Timer Internal Mode Threshold
VTMR Rising
l
V1 – 0.40 V1 – 0.020 V1 – 0.10
V
VTMR(INT)
Timer Internal Mode Hysteresis
VTMR Falling
l
40
100
160
mV
VTMR(LATCH) Timer Latch Mode Threshold
VTMR Falling
l
0.10
0.20
0.40
V
VTMR(LATCH) Timer Latch Mode Hysteresis
VTMR Rising
l
40
75
160
mV
tP,LR
Latch Release Propagation Delay to RST Low
VTMR Rising, Step 0V to 0.6V
l
0.5
3
s
tSU,MON
Monitor Input Setup Time to Latch Enable (Note 7)
Monitor Input Setup Time to Latch Release
VTMR Falling, Step 0.6V to 0V
VTMR Rising, Step 0V to 0.6V
l
2
ms
tHD, MON
Monitor Input Hold Time to Latch Enable
Monitor Input Hold Time to Latch Release
VTMR Falling, Step 0.6V to 0V
VTMR Rising, Step 0V to 0.6V
l
0
s
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
Note 3: The internal supply voltage (VCC) is generated from the greater of
the voltages on the V1 and V2 inputs. VCC = V1 for the LTC2911-5.
Note 4: Under typical operating conditions, quiescent current is drawn
from the greater of the voltages on the V1 and V2 inputs. For the
LTC2911-5 only V1 supplies the quiescent current.
Note 5: The RST and PFO output pins on the LTC2911 have internal pull-
ups to V1. However, for faster rise times or for VOH voltages greater than
V1, use an external pull-up resistor.
Note 6: The RST and PFO pull-down currents are derived from V1 and V2
except for the LTC2911-5 where the pull-down strength is derived only
from V1.
Note 7: tSU,MON is required to latch a low RST state and tSU,MON + tRST is
required to latch a high RST state.
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