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参数资料
| 型号： | LTM4603IV-1#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/26页 |
| 文件大小： | 0K |
| 描述： | IC DC/DC UMODULE 6A 118-LGA |
| 产品培训模块： | Power Module vs. Discrete DC to DC |
| 软件下载： | LTM4603-1 Spice Model |
| 产品目录绘图： | LTM Series_15x15x2.8 |
| 设计资源： | LTM4603IV-1#PBF Footprint.bxl |
| 特色产品： | μModule Products |
| 标准包装： | 119 |
| 系列： | µModule® |
| 类型： | 非隔离（POL） |
| 输出数： | 1 |
| 电压 - 输入（最小）： | 4.5V |
| 电压 - 输入（最大）： | 20V |
| Voltage - Output 1： | 0.6 ~ 5 V |
| 电流 - 输出（最大）： | 6A |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 118-LGA |
| 尺寸/尺寸： | 0.59" L x 0.59" W x 0.11" H（15.0mm x 15.0mm x 2.8mm） |
| 包装： | 托盘 |
| 工作温度： | -40°C ~ 85°C |
| 效率： | 93% |
| 产品目录页面： | 2711 (CN2011-ZH PDF) |
LTM4603/LTM4603-1
APPLICATIONS INFORMATION
V UVLO =
R1 + R2
RunEnable
The RUN pin is used to enable the power module. The
pin has an internal 5.1V Zener to ground. The pin can be
driven with a logic input not to exceed 5V.
The RUN pin can also be used as an undervoltage lock out
(UVLO) function by connecting a resistor divider from the
input supply to the RUN pin:
? 1.5V
R2
See the Simplified Block Diagram (Figure 1).
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point and tracks
with margining.
COMP Pin
the system does not have a 5V power rail, the LTM4603
can be directly powered by Vin. The gate driver current
through the LDO is about 20mA. The internal LDO power
dissipation can be calculated as:
P LDO_LOSS = 20mA ? (V IN – 5V)
The LTM4603 also provides the external gate driver voltage
pin DRV CC . If there is a 5V rail in the system, it is recom-
mended to connect the DRV CC pin to the external 5V rail.
This is especially true for higher input voltages. Do not
apply more than 6V to the DRV CC pin. A 5V output can be
used to power the DRV CC pin with an external circuit as
shown in Figure 16.
Parallel Operation of the Module
The LTM4603 device is an inherently current mode con-
trolled device. Parallel modules will have very good current
sharing. This will balance the thermals on the design. The
voltage feedback equation changes with the variable n as
modules are paralleled:
+ R FB
Thispinistheexternalcompensationpin.Themodulehas
already been internally compensated for most output volt-
ages. Table 2 is provided for most application requirements.
LTpowerCAD is available for control loop optimization.
V OUT = 0.6V
or equivalently,
60.4k
n
R FB
R FB =
V OUT
? 1
PLLIN
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows the internal top MOSFET turn-on
to be locked to the rising edge of an external clock. The
frequency range is ±30% around the operating frequency
of 1MHz. A pulse detection circuit is used to detect a clock
on the PLLIN pin to turn on the phase-locked loop. The
pulse width of the clock has to be at least 400ns and the
amplitude at least 2V. The PLLIN pin must be driven from a
low impedance source such as a logic gate located close to
the pin. During start-up of the regulator, the phase-locked
loop function is disabled.
INTV CC and DRV CC Connection
An internal low dropout regulator produces an internal
5V supply that powers the control circuitry and DRV CC
for driving the internal power MOSFETs. Therefore, if
60.4k
n
0.6V
where n is the number of paralleled modules.
Thermal Considerations and Output Current Derating
The power loss curves in Figures 7 and 8 can be used
in coordination with the load current derating curves in
Figures 9 to 12, and Figures 13 to 14 for calculating an
approximate θ JA for the module with various heat sinking
methods. Thermal models are derived from several tem-
perature measurements at the bench and thermal modeling
analysis. Thermal Application Note 103 provides a detailed
explanation of the analysis for the thermal models and the
derating curves. Tables 3 and 4 provide a summary of the
equivalent θ JA for the noted conditions. These equivalent
θ JA parameters are correlated to the measured values,
4603fb
15
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTM4603IV-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:6A DC/DC μModule with PLL, Output Tracking and Margining |
| LTM4603V | 制造商:LINER 制造商全称:Linear Technology 功能描述:6A DC/DC μModule with PLL, Output Tracking and Margining |
| LTM4603V-1 | 制造商:LINER 制造商全称:Linear Technology 功能描述:6A DC/DC μModule with PLL, Output Tracking and Margining |
| LTM4604 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Low Voltage, 4A DC/DC μModuleTM with Tracking |
| LTM4604A | 制造商:LINER 制造商全称:Linear Technology 功能描述:Low Voltage, 4A DC/DC μModule with Tracking |
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