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参数资料
| 型号： | LV24030LP |
| 元件分类： | 调谐器 |
| 英文描述： | AUDIO TUNER, QCC24 |
| 封装： | 4 X 4 MM, 0.80 MM HEIGHT, VQLP-24 |
| 文件页数： | 2/14页 |
| 文件大小： | 171K |
| 代理商： | LV24030LP |
LV24030LP
No.A1003-10/14
Register 05h-MSRC_SEL-Measurement Source Select Register (Write-only)
7
6
5
4
3
2
1
0
MSR_O
AFC_LVL
DIR_AFC
RST_AFC
MSS_AFCS
MSS_SD
MSS_RF16
MSS_IF
Bit 7
MSR_O: Outputs VCO of IF,SD, and RF frequencies to the data pin (for testing)
0 = No output
1 = Output (for testing)
Bit 6
AFC_LVL: AFC trigger level
0 = AFC is always active
1 = AFC is only active when field strength is above 20dB
μV
Bit 5
DIR_AFC: AFC operation direction
0 = AFC reverse operation (for testing)
1 = AFC normal operation
Bit 4
RST_AFC: AFC reset
0 = Normal operation
1 = Resets AFC to the center of control range
Bit 3
MSS_AFCS: Detects the AFC status by the data line
0 = AFC status read disabled
1 = AFC status read enabled
With this bit set to “1” and with MSR_O = 1, the state outside the AFC control range can be detected from the change of the
DATA line.
In case of the state outside the AFC control range, the DATA line changes from L to H.
Bit 2
MSS_SD: Stereo decoder oscillator measurement
0 = Disable stereo decoder oscillator measurement
1 = Enable stereo decoder oscillator measurement
Bit 1
MSS_RF16: RF/16 measurement
0 = RF/16 oscillator measurement disabled
1 = RF/16 oscillator measurement enabled
Bit 0
MSS_IF: IF oscillator measurement
0 = Disable IF oscillator measurement
1 = Enable IF oscillator measurement
Note: Be sure that only one of MSS_XX bits is enabled.
The FM RF frequency is divided to 1/16 and input into the measuring circuit.
Register 06h-CTRL_STAT-Control Status Register (Read-only)
7
6
5
4
3
2
1
0
REV3
REV2
REV1
REV0
AFC_UP
AFC_DN
COV_FLG
AFC_FLG
Bit 7-4
REV[3:0]: 0Fh
Bit 3
AFC_UP: AFC adjustment up-direction
0 = Center value
1 = RF frequency adjusted in the up-direction
Bit 2
AFC_DN: AFC adjustment down-direction
0 = Center value
1 = RF frequency adjusted in the down-direction
Bit 1
COV_FLG: Counter overflow flag
0 = No overflow
1= Counter overflow
Bit 0
AFC_FLG: AFC out of range bit
0 =AFC is within control range
1 =AFC is out of control range
Note: COV_FLG is cleared when CLR_CNT1 bit of CNT_CTRL register is set to “1.”
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