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参数资料
| 型号： | LV24230LP-A |
| 元件分类： | 调谐器 |
| 英文描述： | 1-BAND, AUDIO TUNER, QCC24 |
| 封装： | 4 X 4 MM, VQLP-24 |
| 文件页数： | 4/17页 |
| 文件大小： | 133K |
| 代理商： | LV24230LP-A |
LV24230LP-A
No.A0891-12/17
Register 11h – TNPH_STAT – Tune position high/status (Read-Only)
7
6
5
4
3
2
1
0
ERROR [2 : 0]
SM_IF
TUNED
NA
TUNEPOS [9 : 8]
bit 7-5 :
ERROR [2 : 0] : Error Code
ERROR [2 : 0]
Remark
0
OK, Command end (No Error)
1
Default value after or during reset
2
Band Limit Error
3
DAC Limit Error
6
Command forced End
7
Command busy
bit 4 :
SM_IF : Command End interrupt flag
0 = No Interrupt
1 = Interrupt
This bit is set when the command is over. When the IRQ pin interrupt is allowed, the pin status is changed, Reading this register causes clearing.
bit 3 :
TUNED : Radio tuning Flag
0 = No tune
1 = Tuned
Note : This flag is set when Tuned or a station search succeeded.
This flag is cleared under 3 conditions as below.
(1) PW_RAD = 0
(2) Tuning Frequency
(3) FM station searching
bit 2 :
NA : 0 (Fix)
bit 1 : 0 :
TUNEPOS [9 : 8] : Current RF frequency (High 2 bit)
Register 19h – REF_CLK_PRS – Reference clock prescaler (Read/Write)
7
6
5
4
3
2
1
0
REFPRE [2 : 0]
REFMOD [4 : 0]
bit [7 : 5] :
REFPRE [2 : 0] : Reference Clock pre- scaler
0 = 1 : 1
1 = 1 : 2
…
7 = 1:128
bit [4 : 0] :
REFMOD [4 : 0] : 5-bit slope correction
Register 1Ah – REF_CLK_DIV – Reference clock divider (Read/Write)
7
6
5
4
3
2
1
0
REFDIV [7 : 0]
Bit 7-0 :
REFDIV [7 : 0] : Reference Clock Divider
0 : Divider Value = 1
1 : Divider Value = 2
…
255 : Divider Value = 256
Register 1Bh –REF_CLK_OFF – Reference clock offset (Read/Write)
7
6
5
4
3
2
1
0
REFOFFS [7 : 0]
Bit 7-0 :
REFOFFS [7 : 0] : Offset register for the spread of reference clock
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