参数资料
型号: LV3328PM
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封装: 10 X 10 MM, QIP-44
文件页数: 12/26页
文件大小: 257K
代理商: LV3328PM
LV3328PM
No.A1657-2/26
Continued from preceding page.
Middle control :
The middle control gain can be maximum boost +20dB position and maximum cut -20dB position.
( +20dB to -20dB in 1dB steps.)
The middle control center frequency 700Hz/1KHz/1.2KHz can be selected.
The middle control quality factor 1.0/2.0 can be selected.
Treble control :
The treble control gain can be maximum boost +20dB position and maximum cut -20dB position.
( +20dB to -20dB in 1dB steps.)
The treble control center frequency 7KHz/10KHz/11KHz/12KHz can be selected.
The treble control quality factor 1.0/2.0 can be selected.
Fader control :
A total of 81 positions from 0 to -79dB in 1dB steps and -
∞dB.
Independent control each four channels output
General-purpose ports control :
Mono / stereo selection.
A total of 81 positions from 0 to -79dB in 1dB steps and -
∞dB.
Fader-front output mix / general purpose output selection.
Input switching control block / general purpose input selection .
Mute
Specifications
Absolute Maximum Ratings
at Ta = 25
°C, VSS = 0V
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VDD max
VDD
10
V
Maximum input voltage
VIN max
All input pins
VSS-0.3 to VDD
V
Allowable power dissipation
Pd max
Ta
≤ 85°C, when mounted on a printed circuit
board *
600
mW
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-50 to +125
°C
* Specified circuit board : 114.3
×76.1×1.6mm3 : glass epoxy board
Allowable Operating Ratings
at Ta = 25
°C, VSS = 0V
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
VDD
7.0
9.0
9.5
V
High-level input voltage
VIH
DATA, CLK, LEVDET
3.0
5.5
V
Low-level input voltage
VIL
DATA, CLK, LEVDET
VSS
1.0
V
Input pulse width
T
φW
CLK
0.6
μs
Setup time
Tsetup
DATA, CLK
0.1
μs
Hold time
Thold
DATA, CLK
0.9
μs
Operating frequency
fopg
CLK
400
kHz
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