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参数资料
| 型号： | LV5103LP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封装： | 5 X 5 MM, VQLP-40 |
| 文件页数： | 9/11页 |
| 文件大小： | 123K |
| 代理商： | LV5103LP |
LV5103LP
No.A0585-7/11
Block Diagram
The three power supply pins VBAT1, VBAT2, and VBAT3 must be shorted together externally.
The three ground pins GNDM, PGND, and GNDSWREG must be shorted together externally and must always be at a
potential that is the lowest potential in the system.
VBAT1
BGR
RREF
LDO1O
LDO2O
LDO3O
LDO5O
LDO8S
VBAT3
SWOUT1
PGND
GNDSWREG
LDO4O
VBAT2
LDO6O
LDO6S
VBATL6
LDO7O
GNDM
LDO2S
LDO3B
SWCTL
FBIN
RFPDN
VBATDET
↑3.2V ↓2.4V
ON/OFF_1
DELAY
RESETO
STCLR
PS
ON/OFF_1
ON/OFF_2
VBAT1
ON/OFF_1
ON/OFF_2
ON/OFF_1
PS
VBAT3
ON/OFF_1
PS
ON/OFF_1
PS
2.2
F
2.2
F
2.2
F
2.2
F
2.2
F
0.1
F
0.1
F
2.2
F
2.2
F
2.2
F
10
F
10
F
4.7
H
0.01
F
1
A
85k
40k
LDO4S
VBAT1
VBATL8
LDO8O
PS
LDO3S
VBATL7
ON/OFF_1
DQ
CQ
R
VBAT1
BVLT
BVLTON
VBAT1
LDO2
VBAT1
RESETO
STATUS
ADPTDETIN
PKEYDET
PWRKEY
PWRHOLD
PWRSAVE
LDO1
1.5V
30mA
LDO2
2.85V/
200mA
LDO3
2.85V/
150mA
LDO4
3.1V/
450mA
LDO5
3.3V/
150mA
LDO7
1.8V/
150mA
LDO6
1.5V/
200mA
LDO8
1.2V/
500mA
DC/DC1
2.4V/
800mA
DET
2.4V
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