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参数资料
| 型号： | LV5608LP |
| 厂商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHED CAPACITOR REGULATOR, 2500 kHz SWITCHING FREQ-MAX, QCC24 |
| 封装： | 3.50 X 3.50 MM, VCT-24 |
| 文件页数： | 6/8页 |
| 文件大小： | 158K |
| 代理商： | LV5608LP |
LV5608LP
No.A0691-6/8
External clock signal startup sequence
EN Pin and VDD
Though the sequence operation is made at startup, startup is not effectuated if the internal circuit has not been reset.
To reset the internal circuit, it is necessary to keep the EN pin at L till VDD becomes 3V or more.
Note that operation with VDD and EN pin short-circuited cannot be made.
Since the sequence operation is incorporated for stop of operation, the charge pump remains active till 7.5ms (max)
passes after setting the EN pin to L. During this period, VDD must be kept at 3V or more to allow the internal sequence
logic to operate correctly.
EN
CLK
Regulator
(C22)
SEL
S0
S1
* Internal 1 MHz
9.4ms(min)
Internal clock
started at 1 MHz
Charge pump
(C23)
* IC internal signal
V
DD
Set EN = H by setting V
DD
at 3 V or more.
Frequency selection
External clock selected
SEL=L (Internal clock)
SEL=H (External clock)
Do not attempt change the signal after 9.4 ms from EN = H.
* CP clock 1/2
φ
* CP clock 1/4
φ
* CP clock 1/8
φ
* CP clock 1/16
φ
Never set V
DD
at 3 V or less till the
sequence is over (7.5 ms after EN = L).
Steady operation
Stop
sequence
7.5ms(max)
9.4ms(min)
Stop at EN = L or over-current protection
* CP clock 1MHz
* CP clock 500kHz
* CP clock 250kHz
* CP clock 125kHz
Frequency selection
Do not attempt change the signal after 9.4 ms from EN = H.
External clock selected
Internal clock
started at 1 MHz
Steady operation
Stop
sequence
7.5ms(max)
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