参数资料
型号: LV5749NV-TLM-E
厂商: ON Semiconductor
文件页数: 4/6页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-SSOP
标准包装: 2,000
PWM 型: 电流模式
输出数: 1
频率 - 最大: 140kHz
电源电压: 8.5 V ~ 42 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-LSSOP(0.175",4.40mm 宽)
包装: 带卷 (TR)
LV5749NV
Block Diagram
VIN 14
MODE 12
5 μ A
5V
REGULATOR
REFERENCE
VOLTAGE
UVLO
OCP 13
1.25V
+
-
OCP Comp1
OSP
LOGIC
ILIM 15
MODE L 18.5 μ A
MODE H 37 μ A
-
+
OCP Comp2
VCC
+
S
R
Q
7 CBOOT
5 μ A
-
Current
Amp
8 HDRV
SS 16
FB 1
COMP 2
0.67V
SD
+
+
-
Err
Amp
SAW WAVE
OSCILLATOR
DMAX = 90%
1.0V
0.5V
-
+
PWM Comp
CONTROL
Logic
5V
6 SW
10 VDD
9 LDRV
shut down(SD)
11 GND
4
5
3
Pin Function
RT SYNC
EN
Pin No.
14
11
10
7
6
5
9
8
1
2
16
15
3
13
4
12
Pin name
VIN
GND
VDD
CBOOT
SW
SYNC
LDRV
HDRV
FB
COMP
SS
ILIM
EN
OCP
RT
MODE
Description
Power supply pin.
This pin is monitored by UVLO function. When the voltage of this pin becomes 7.7V or more by UVLO function, The IC starts
and the soft start function operates.
Ground pin. Each reference voltage is based on the voltage of the ground pin.
Power supply pin for an external the lower MOS-FET gate drive.
Bootstrap capacity connection pin. This pin becomes a GATE drive power supply of an external NchMOSFET.
Connect a bypath capacitor between CBOOT and SW.
Pin to connect with switching node. The source of NchMOSFET connects to this pin.
External synchronous signal input pin.
An external the lower MOSFET gate drive pin.
An external the upper MOSFET gate drive pin.
Error amplifier reverse input pin.
By operating the converter, the voltage of this pin becomes 0.67V.
The voltage in which the output voltage is divided by an external resistance is applied to this pin.
Error amplifier output pin.
Connect a phase compensation circuit between this pin and GND.
Pin to connect a capacitor for soft start. A capacitor for soft start is charged by using the voltage of about 5 μ A.
This pin ends the soft start period by using the voltage of about 1.1V and the frequency fold back function becomes
active.
Reference current pin for current detection.
The sink current of about 20 μ A flows to this pin when Low level (GND) is set to the MODE pin.
Also, the sink current of about 40 μ A flows to this pin when High level (VIN) is set to the MODE pin.
When a resistance is connected between this pin and VIN outside and the voltage applied to the SW pin is lower than the
voltage of the terminal side of the resistance, the upper NchMOSFET is off by operating the current limiter comparator. This
operation is reset with respect to each PWM pulse.
ON/OFF pin.
Pin to set the time of the timer (during double the over current detection point)
Connect a capacitor between this pin and GND. OCP charge current : 5 μ A
Pin to set the oscillation frequency. Connect a resistance between this pin and GND.
Pin to switch the over current detection point. Set by the low level (GND) of the ILIM pin.
Set by the high level (VIN) of the OCP pin.
When this MODE pin is set to the high level and the point of the over current detection is set by using the ILIM pin is exceeded,
the value becomes double the original value.
Also, when the MODE pin is set to the low level, the point of the over current detection remains an original value.
No.A1684-4/6
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