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参数资料
| 型号： | LV761132F |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | 20 X 14 MM, QIP-80 |
| 文件页数： | 3/16页 |
| 文件大小： | 187K |
| 代理商： | LV761132F |
LV761132F
No.A1398-11/16
Serial Characteristics (Micro-computer Chip SIO0) *1 at Ta
= -10°C to +65°C, VSS = 0V
Ratings
Parameter
Symbol
Pins
Conditions
VDD [V]
min
typ
max
Unit
Cycle
tSCK (1)
2
tCYC
Low level pulse-width
tSCKL (1)
1
tCYC
tSCKH (1)
See the figure 4.
1
tCYC
Inpu
tclock
High level pulse-width
tSCKHA (1a)
SCK0 (P02)
Continuous data
transmitting and receiving
mode
See the figure 4. (*2)
4.5 to 5.5
4
tCYC
Cycle
tSCK (2)
4/3
tCYC
Low level pulse-width
tSCKL (2)
1/2
tSCK
tSCKH (2)
At the CMOS output
selection
See the figure 4.
1/2
tSCK
Serial
clock
Outp
ut
clock
High level pulse-width
tSCKHA (2a)
SCK0 (P02)
At the CMOS output
Continuous data
transmitting and receiving
mode
See the figure 4.
4.5 to 5.5
tSCKH (2)+
2tCYC
tSCKH (2)+
(10/3) tCYC
tCYC
Data setup time
tsDI (1)
0.03
μs
Ser
ial
inp
u
t
Data hold time
thDI (1)
SI0 (P01)
SB0 (P01)
Define for rising of
SIOCLK.
See the figure 4.
4.5 to 5.5
0.03
μs
tdDO (1)
SO0 (P00)
Continuous data
transmitting and receiving
mode (*3)
(1/3) tCYC
+0.05
μs
Inpu
tclock
tdDO (2)
Synchronous 8-bit mode
(*3)
1tCYC+0.05
μs
Ser
ial
ou
tpu
t
Outp
ut
clock
Output delay time
tdDO (3)
(*3)
4.5 to 5.5
(1/3) tCYC
+0.05
μs
(*1) This limited value is theoretical figure. Be sure to ensure the margin in accordance with use situation.
(*2) When using the serial clock input with continuous data transmitting and receiving mode, lengthen time from the set of the cereal clock of SI0RUN in the
state of "H" to the falling of the first cereal clock when it begins to send and receive continuous data more than tSCKHA.
(*3) This is defined for falling of SIOCLK and it is defined as time until output change start in open drain output. (See the figure 4)
Serial Characteristics (Micro-computer Chip SIO1) *4 at Ta
= -10°C to +65°C, VSS = 0V
Ratings
Parameter
Symbol
Pins
Conditions
VDD [V]
min
typ
max
Unit
Cycle
tSCK (3)
2
tCYC
Low level pulse-width
tSCKL (3)
1
tCYC
Inpu
tclock
High level pulse-width
tSCKH (3)
SCK1 (P15)
See the figure 4.
4.5 to 5.5
1
tCYC
Cycle
tSCK (4)
2
tCYC
Low level pulse-width
tSCKL (4)
1/2
tSCK
Serial
clock
Outp
ut
clock
High level pulse-width
tSCKH (4)
SCK1 (P15)
At the CMOS output
selection
See the figure 4.
4.5 to 5.5
1/2
tSCK
Data setup time
tsDI (2)
0.03
μs
Ser
ial
inp
u
t
Data hold time
thDI (2)
SI1 (P14)
SB1 (P14)
Define for rising of
SIOCLK.
See the figure 4.
4.5 to 5.5
0.03
μs
Ser
ial
ou
tpu
t
Output delay time
tdDO (4)
SO1 (P16)
SB1 (P14)
Define for falling of
SIOCLK.
Define as time until output
change start in open drain
output.
See the figure 4.
4.5 to 5.5
(1/3) tCYC
+0.05
μs
(*4) This limited value is theoretical figure. Be sure to ensure the margin in accordance with use situation.
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