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参数资料
| 型号： | LX1571CDMT |
| 厂商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分类： | 稳压器 |
| 英文描述： | 1 A SWITCHING CONTROLLER, PDSO8 |
| 封装： | PLASTIC, SOIC-8 |
| 文件页数： | 12/12页 |
| 文件大小： | 257K |
| 代理商： | LX1571CDMT |
PHASE MODULATED AC SYNCHRONOUS SECONDARY-SIDE CONTROLLER
LX1570/1571
PRODUCT DA T ABOOK 1996/1997
9
Copyright 1997
Rev. 0.9.3
1/97
P RELIMINAR Y D AT A S HEET
IC DESCRIPTION
C
.
F
T =
+
=
1
0 6 80 10
1
310
1
35 10
0 033
3
33
.
CURRENT LIMITING
Using the main Block Diagram as a reference and the typical
application circuit of Figure 2, note that current limiting is per-
formed by sensing the current in the return line using a current
transformer in series with the switch. The voltage at C.S. pin is
then amplified and compared with an internal threshold. Ex-
ceeding this threshold turns the output drive off and latches it off
until the set input of the PWM latch goes high again. However,
if the current keeps rising such that it exceeds the HICCUP com-
parator threshold, or if the output of the converter drops by
≈20% from its regulated point, two things will happen. First, the
HICCUP comparator pulls C
T pin to 6V, which keeps the output
drive off and causes C
T charging current to be disconnected.
Second, it sets the HICCUP latch, causing the discharge current
to be turned off until the C
T capacitor voltage goes below 0.3V.
Since both charge and discharge currents are disconnected from
the capacitor, the only discharge path for C
T is the inter nal 2A
current source. When this happens, a very slow discharge oc-
curs, resulting in a long delay time between current limit cycles
which greatly reduces power MOSFET dissipation under short
circuit conditions.
V
START UP Cap
16V
t
ST
10V
V
O
V
O
OUT DRV
V
CAP
FIGURE 5 — LX157x V
CC START-UP VOLTAGE TIMING DIAGRAM
1ms / Div.
Output
Voltage - 5V / Div.
Soft-Start
Voltage - 1V / Div.
COMP Pin
L1 Current
t
RAMP
FIGURE 6 — START-UP TIMING DIAGRAM
TIMING SECTION
A capacitor connected from the C
T pin to ground performs sev-
eral functions. First, it sets the OUT DRV duty cycle to a constant
54% (regardless of the C
T value) in order to: a) provide the gate
drive for an N-channel MOSFET, utilizing a simple gate drive
transformer, and b) insure reliable operation with a transformer
duty cycle within a 0 to 50% range. Second, it sets the free-
running frequency of the converter in order to insure the con-
tinuous operation during non-steady state conditions, such as
start up, load transient and current limiting operations. The value
of the timing capacitor is selected so that the free-running fre-
quency is always 20% below the minimum operating frequency
of the secondary transformer voltage, insuring proper operation.
Equation 4 shows how to select the timing capacitor C
T.
Equation 4
where: V
RPP
≡ Peak to peak voltage of C
T (0.6V typ.)
f
S
≡ Free-running frequency of the converter.
Selected to be 80% of the minimum freq.
of the seconday side transformer voltage.
I
CHG
≡ C
T charging curr ent (3mA typ.)
I
DISCH ≡
C
T discharge current (3.5mA typ.)
Example: Assuming the transformer frequency is at 100kHz,
V
RPP = 0.6V, ICHG = 3mA, IDISCH = 3.5mA.
C
Vf
II
T
RPP
S
CHG
DISCH
=
+
1
11
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