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参数资料
| 型号： | LX1673-09CPW |
| 英文描述： | PWM Controllers |
| 中文描述： | PWM控制器 |
| 文件页数： | 19/21页 |
| 文件大小： | 554K |
| 代理商： | LX1673-09CPW |
Microsemi
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 19
Copyright
2000
Rev. 0.5i, 2002-07-17
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LX1671
Multiple Output LoadSHARE PWM
P
RELIMINARY
I N T E G R A T E D P R O D U C T S
APPLICATION NOTE
CONSIDERATIONS
1. The power N-MOSFET transistor’s total gate charge spec,
(Qg) should not exceed 40Nc when VCx = +12V. This
condition will guarantee operation over the specified ambient
temperature range. The Qg value of the N-MOSFET is
directly related to the amount of power dissipation inside the
IC package, from the three sets of MOSFET drivers. The
equation relating Qg to the power dissipation of a MOSFET
driver is: Pd = f * Qg * Vd . f = 300KHs and Vd is the
supply voltage for the MOSFET driver. The three bottom
MOSFET drivers are powered by the VCCL pin that is
connected to +5V. The upper MOSFET drivers can be
connected to the +12V supply or to a bootstrap supply
generated by it’s output bridge. The bootstrap supply will be
at +17V. Depending on the thermal environment of the
application circuit, the Qg value of the N-MOSFETs will have
to be less than the 40nC value. A typical configuration of the
input voltage rails to generate the output voltages required is
having the 5volt supply on phase 1, the 3.3volt supply on
phase 2, and the 12volt supply on phase 3. At the max Qg
value, the three bottom MOSFET drivers will dissipate 60mw
each. The upper MOSFET drivers for phases 1 and 2 will
operate off of +12volts. Their dissipation is 144mw each.
Phase 3 will have the bootstrap supply so its dissipation is
204mw. The total power dissipation for gate drive is 672mw.
Icc x Vcc =15ma x 5 V= 75mW. Total package power
dissipation = 747mW. Using the thermal equation of : Tj =
Ta + Pd * Oja, the Junction temperature for this IC package is
= 23 + .747 * 85 which = 86 deg C. This means that the
ambient temperature rise has to be less than 64 deg C.
2. The Soft-Start reference input has a 300mv threshold, above
which the PWM starts to operate. The internal operating
reference level is set at 800mv. This means that the output
voltage is 37.5% low when the PWM becomes active. This
starts each phase up in the current limit mode without Hiccup
operation. If more than one phase is using the 5volt rail for
conversion, then their soft-start capacitor values should be
changed so that the two phases do not start up together. This
will help reduce the amount of 5volt input capacitance
required. Also the VCC pin and the VCCL pin should be kept
separated and should be decoupled separately. This will
prevent the VCC pin from drooping back below the UVLO set
point during start up.
3. If a phase is not used connect the VSX and VCX pins to
VCC. Do not leave them floating. A floating VSX pin will
result in operation resembling a hiccup condition.
4. When phases 1 and 2 are used in the Bi-phase mode to
current share into the same output load, the phase 2 current is
forced to follow the phase 1 current. It is important to use a
larger soft-start capacitor on phase 2 than phase 1 so that the
phase 1 current becomes active before phase 2 becomes active.
This will minimize any start up transient. It is also important
to disable phase 1 and 2 at the same time. Disabling phase 1
without disabling phase 2, in the Bi-phase mode, lets phase 2
turn on and off randomly because it has lost its reference.
5. The maximum output voltage when using LoadSHARE is
limited by the input common mode voltage of the error amplifier
and cannot exceed the input common mode voltage.
6. The minimum R
SET
resistor value is 1k ohm for the current
limit sensing. If this resistor becomes shorted, it will do
permanent damage to the IC.
7. A resistor has been put in series with the gate of the LDO pass
transistor to reduce the output noise level. The resistor value
can be changed to optimize the output transient response versus
output noise.
8. The LDO controller inside the IC uses the voltage at VC1 as
the drive voltage. Due to noise considerations ideally the
voltage on the VC1 pin would be a fixed +12volt supply. When
VC1 is connected to a bootstrap supply the LDO output will
reflect significant switching noise without filtering. When VC1
is generated with a bootstrap supply the LDO should not be
used.
9. To delay the turn on of the LDO controller output, a capacitor
should be connected between the LDDIS pin and the +5volts.
The LDDIS input has a 100K pull down resistor, which keeps
the LDO active until this pin is pulled high. During the power
up sequence the capacitor connected to the LDDIS pin will keep
the LDO off until this capacitor, being charge by the 100K pull
down resistor, goes through the low input threshold level.
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