参数资料
型号: LX1801CLQ-TR
厂商: MICROSEMI CORP
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PQCC16
封装: 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MLPQ-16
文件页数: 8/12页
文件大小: 255K
代理商: LX1801CLQ-TR
LX1801
PRODUCTION DATA SHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 5
Copyright
2005
Rev. 1.0, 5/4/2006
WWW
.Microse
m
i
.CO
M
SMBus to Analog & Digital System Interface
TM
APPLICATION NOTE
The LX1801 is a seven register device that uses SMBus
commands to communicate with the host system. All registers are
defined as full byte wide with reserved (undefined) bits containing a
default value of “0”. Four of the seven registers are read / write, and
three are read only with respect to the SMBus.
SMB PROTOCOL
Only standard SMBus protocol, version 2.0 or higher, may be
used for this device. The only required commands are the SMBus
Read Byte and the SMBus Write Byte protocols. There are to be no
non standard protocols implemented. Further, register contents shall
not be altered by invalid commands.
General Rules for Writing and Reading LX1801 Registers with
the SMBus.
Writes to registers can be performed by either the SMBus Write
Byte protocol and / or by internal IC logic, depending on the register
type (see table 1).
Reads can be performed on all seven registers by issuing the
Read_Byte protocol.
Read Only registers can be written only by internal logic. Their
contents can not be affected by SMBus write commands.
Specific Requirements for SMBus Protocols:
The IC shall implement the SMBus Read Byte protocol.
The IC shall implement the SMBus Write Byte protocol.
The IC shall not require the use of any other SMBus protocol to
meet the requirements contained in the Dell M07 specification.
The IC shall operate correctly when the SMBus master clock
operates at a frequency of 55KHz and over the complete
frequency range of 10KHz to 100KHz.
The IC shall not employ clock stretching.
The IC shall not include SMBus pull up resistors. These are
provided by the host system.
Read Byte Protocol:
S
Slave Address
Wr
A
Command Code
A
S
Slave Address
Rd
A
Data Byte
P
1
7
1
8
1
7
1
8
1
Write Byte Protocol:
S
Slave Address
Wr
A
Command Code
A
Data Byte
P
1
7
1
8
1
8
1
Grey shading represents cycles during which the LX1801 “owns” or “drives” the Data line. All other cycles are driven by the host.
Definitions
S:
Start condition
Wr:
Write
Rd:
Read
A:
Acknowledge
P:
Stop Condition
Protocol must be per standard SMB specification version 2.0 or higher.
AA
PP
LL
IICC
AA
TT
IIOO
NN
SS
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