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参数资料
| 型号： | LX64EV-5FN100I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 8/9页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH DIGITAL 100FPBGA |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 176 |
| 功能： | 开关 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LBGA |
| 供应商设备封装： | 100-FPBGA（11x11） |
| 包装： | 托盘 |
Lattice Semiconductor
ispGDX2 Family Data Sheet
5
Figure 2. GDX Block
The output register of the MRB has a built-in bi-directional shift register capability. Each output register correspond-
ing to MRB “n”, receives data output from its two adjacent MRBs, MRB (n-1) and MRB (n+1), to provide shift regis-
ter capability. Like the output register, each input register of the MRB has built-in shift register capability. Each input
register can receive data from its two adjacent MRB input registers, to provide bi-directional shift register capability.
The chaining crosses GDX Block boundaries. The chain of input registers and the chain of output registers can be
combined as one shift register via the GRP.
MUX and Register
Block (MRB)
0
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
MUX and Register
Block (MRB)
1
MUX and Register
Block (MRB)
2
GDX Block
GRP
sysIO Bank
32 bits
Control
MUX
Select
16 bits
4 bits
8
2
MUX and Register
Block (MRB)
3
Control Array
8
2
8
2
8
2
8
2
8
2
4
Nibble 3
MRBs 12-15
Nibble 2
MRBs 8-11
Nibble 1
MRBs 4-7
Nibble 0
SELECT
DEVICES
DISCONTINUED
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相关代理商/技术参数 |
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