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参数资料
| 型号： | LXT336QE |
| 英文描述： | PCM RECEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|64PIN|PLASTIC |
| 中文描述： | 的PCM接收机|四|优税PCM-30/E-1 |的CMOS | QFP封装| 64管脚|塑料 |
| 文件页数： | 14/32页 |
| 文件大小： | 395K |
| 代理商： | LXT336QE |
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LXT331
—
Dual T1/E1 Line Interface Unit
14
Datasheet
2.3.1.2
Serial Output Word
Figure 6
shows the Serial Output data structure. SDO is high impedance when SDI receives an
Address/Command byte. If SDI receives a write command (R/W = 0), SDO remains in high
impedance. If the command is a read (R/W = 1), then SDO becomes active after the last Command/
Address bit (A6) and remains active for eight SCLK cycles. Typically the first bit out of SDO
changes the state of SDO from high Z to a Low/High. This occurs approximately 100 ns after the
eighth following edge of SCLK.
The output data byte reports DPM and DFM conditions, equalizer settings, and operating modes
(normal or diagnostic). The first 5 bits (D0-4) report DPM and DFM status and the Line Length
Equalizer settings. The last 3 bits (D5-7) report operating modes and interrupt status as defined in
Table 4
.
If the INT line for the respective port is High (no interrupt is pending), bits D5-7 report the
operating modes listed in
Table 4
. If the INT line for the respective port is Low, the interrupt status
overrides all other reports and bits D5-7 reflect the interrupt status as listed in
Table 4
.
2.3.1.3
Interrupt Handling
The Host mode provides two latched Interrupt output pins, INT0 and INT1, one for each LIU. An
interrupt is triggered by a change in the DPM or DFM bit (D0=DPM, D1=DFM). As shown in
Figure 7 on page 17
, either or both interrupt generators can be masked by writing a 1 to the
corresponding bit (D0 or D1) of the input data byte. When an interrupt occurrs, the INT output pin
is pulled Low. The output stage of each INT pin consists of a pull-down device; thus an external
pull-up resistor is required. Clear the interrupts as follows:
1. If one or both interrupt bits (DPM or DFM of the output data byte) are High, write a 1 to the
corresponding bit of the input data byte to clear the interrupt. Leave a 1 in either bit position to
effectively mask that interrupt. To re-enable the interrupt capability, reset either D0 or D1 or
both to 0.
2. If neither DPM nor DFM is high, reset the chip to clear the interrupt. To reset the chip, set data
input bits D5 and D6 = 1, and D7 = 0.
2.3.2
Hardware Mode Control
Hardware control is the default operating mode. The LXT331 operates in Hardware mode unless a
clock is applied to the LEN21/SPE pin. In Hardware mode, the SIO pins are re-mapped to provide
control functions. In Hardware mode, the PMRK/NMRK outputs are valid on the rising edge of
RCLK.
Table 3. SIO Input Bit Settings
(See
Figure 5
)
Mode
TST
bit D5
ALOOP
bit D6
TAOS
bit D7
Analog Loopback
0
1
0
Transmit All Ones
0
X
1
Reset/High Z
1
1
0
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