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参数资料
| 型号： | LZ34B1B |
| 厂商： | SHARP ELECTRONICS CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQCC36 |
| 封装： | 0.425 INCH, LCC-36 |
| 文件页数： | 13/15页 |
| 文件大小： | 144K |
| 代理商： | LZ34B1B |
PRELIMINARY
LZ34B1B
7
TIMING CHART
[Normal Mode]
CLK
ADOUT
(D0-D7)
Normal
HD
CLK
ADOUT
(D0-D7)
776
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
HORIZONTAL PULSE TIMING
PHASE RELATIONS BETWEEN DIGITAL OUTPUT (ADOUT) AND CLOCK (CLK)
VERTICAL PULSE TIMING
ππππππππππππππ
Mirror
10
5
CLK
ADOUT
(D0-D7)
Normal
HD
74
78
82
86
90
94
98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170
OB
1
OB
510
15
20
25
30
35
40
Mirror
ADOUT
(D0-D7)
Normal
Mirror
780
HD
SCLK
SDI
AGC
VD
524 525 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SDI, SCLK, LOAD
Forbidden Period
37 38
6
5
4
3
2
1
OB
7
39
523
493 OB OB OB
492
D0
D10
D20
D30
D37
SYMBOL
MIN.
TYP.
MAX.
UNIT
t
45
ns
488
489
490
491
492
493
OB
487
1 OB OB OB
2
LOAD
SERIAL DATA TIMING (SDI, SCLK, LOAD)
Fixed
Gain
Shutter
Offset
t
012
The rising edge of the HD pulse must be between two rising edges of CLK (0) and CLK (1).
The falling edge of the HD pulse must be between two rising edges of CLK (78) and CLK (79).
The rising edge and falling edge of the VD pulse must be in high period of the HD pulses.
Data in SDI are taken at the rising edge of SCLK.
Clock frequency of SCLK should be less than 1/2 of that of CLK.
Do not insert the SDI, SCLK and LOAD pulses between 28H* and 29H*. Refer to "VERTICAL PULSE TIMING".
Refer to "SERIAL DATA INPUTS" for the contents of serial data from D0 to D37.
* It means ordinal number of the HD pulse.
645
650
OB
655
OB
650 645
640
635
630
625
620 615
OB
πππππππππππππππ
OB
πππππππππππππππ
1
OB
655
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