参数资料
型号: M1A3P1000L-1FGG484I
厂商: Microsemi SoC
文件页数: 5/12页
文件大小: 0K
描述: IC FPGA M1 1KB FLASH 1M 484FBGA
标准包装: 40
系列: ProASIC3L
RAM 位总计: 147456
输入/输出数: 300
门数: 1000000
电源电压: 1.14V ~ 1.575 V
安装类型: 表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 484-BGA
供应商设备封装: 484-FPBGA(23x23)
ARM CortexTM-M1
2P ro d u c t B r i e f
Figure 1 shows an ARM Cortex-M1 processor with debug block diagram.
The NVIC is closely coupled to the ARM Cortex-M1 core
to achieve low-latency interrupt processing. The versions
currently available for use in M1 devices support 1
interrupt with 4 levels of priority. Future versions will
support up to 32 interrupts. To simplify software
development, the processor state is automatically saved
on interrupt entry, and restored on interrupt exist, with
no instruction overhead.
The ARM Cortex-M1 Thumb instruction set’s 16-bit
instruction length allows it to approach twice the density
in memory of standard 32-bit ARM code while retaining
most of the ARM performance advantage over a
traditional 16-bit processor using 16-bit registers. This is
possible because Thumb code operates on the 32-bit
register set in the processor. Thumb code is able to
provide up to 65% of the code size of ARM, and 160% of
the performance of an equivalent ARM processor
connected to a 16-bit memory system.
Figure 1 Processor with Debug Block Diagram
Processor with Debug
AHB-PPB
NVIC
Debug Subsystem
AHB Decoder
AHB Multiplexer
AHB Matrix
Debug ITCM Interface
Debug DTCM Interface
Breakpoint Unit
Data Watchpoint Unit
Debug Control
ROM Table
Internal PPB Signals
External Bus Signals
DAP
AHB-AP
SWJ-DP
Memory Interface
ITCM
DTCM
Core
Dbg
AHB Master
NVIC Interrupt Interface External Interface
Debug Port
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