参数资料
| 型号： | M1A3P400-1PQG208I |
| 厂商： | Microsemi SoC |
| 文件页数： | 2/12页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1KB FLASH 400K 208-PQFP |
| 标准包装： | 24 |
| 系列： | ProASIC3 |
| RAM 位总计： | 55296 |
| 输入/输出数： | 151 |
| 门数： | 400000 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
ARM CortexTM-M1
10
Prod uct Bri e f
Bus Functional Model (BFM)
Introduction
During the development of an FPGA-based SoC, there
are various stages of testing that can be undertaken. This
can involve some, or all, of the following approaches:
Hardware simulation using Verilog or VHDL
Software simulation using a host-based instruction
set simulator (ISS) of the SoC’s processor
Hardware and software co-verification using a
full-functional model of the processor in Verilog,
VHDL or SWIFT form, or using a tool such as
Seamless
BFM Usage Flow
The BFM acts as a pin-for-pin replacement of the
Cortex-M1 in the simulation of the SoC subsystem. It
initiates bus transactions on the native ARM Cortex-M1
bus, which are cycle-accurate with real bus cycles that
ARM Cortex-M1 would produce. It does not have the
ability, however, to implement real ARM Cortex-M1
instructions. The BFM may be used to run a basic test
suite of the SoC subsystem, using the skeleton system
testbench.
You can edit the SoC Verilog/VHDL to add new design
blocks. You can also fill out the system-level testbench to
include tasks that test any newly added functionality, or
add stubs to allow more complex system testing
involving the IP cores. The BFM input scripts can also be
manually enhanced to test out access to register
locations in newly added logic. In this way, you can
provide stimuli to the system from the inside (via the
ARM Cortex-M1 BFM), as well as from the outside (via
testbench tasks).
Timing Shell
There is a timing shell provided for each ARM Cortex-M1
variant wrapped around the BFM. Therefore, the BFM is
bus cycle accurate, and performs setup/hold checks to
model output propagation delays.
Debug
The ARM Debug Architecture uses a protocol converter
box to allow the debugger to talk directly to the core via
a JTAG port. In effect, the scan chains in the core that are
required for test are re-used for debugging. The core
uses the scan chains to insert instructions directly into
ARM Cortex-M1. The instructions are executed on the
core and depending on the type of instruction that has
been inserted, the core or the system state can be
examined, saved, or changed. The architecture has the
ability to execute instructions at a slow debug speed or
to execute instructions at system speed.
In debug mode, the user can perform the following
functions:
Core halt
Core stepping
Core register access
Read/Write to TCMs
Read/Write to AHB address space
Breakpoint
Watchpoints
The main debug components are the following:
Debug control registers – to access and control
debugging of the core
Breakpoint Unit (BPU) – to implement breakpoints
Data Watchpoint Unit (DW) – to implement
watchpoints and trigger resources
Debug memory interfaces – to access external
ITCM and DTCM
ROM table
相关PDF资料 |
PDF描述 |
|---|---|
| IDT71256SA25TPG | IC SRAM 256KBIT 25NS 28DIP |
| IDT71256SA20TPG | IC SRAM 256KBIT 20NS 28DIP |
| A3P400-1PQ208I | IC FPGA 1KB FLASH 400K 208-PQFP |
| IDT71V256SA10YG | IC SRAM 256KBIT 10NS 28SOJ |
| IDT71124S15YG | IC SRAM 1MBIT 15NS 32SOJ |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M1A3P400-1VQ144 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-1VQ144ES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-1VQ144I | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-1VQ144PP | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-1VQG144 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
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